互鎖時間 的英文怎麼說

中文拼音 [hùsuǒshíjiān]
互鎖時間 英文
interlock time
  • 互 : 代詞（相互;彼此） each other; mutual
  • 鎖 : Ⅰ名詞1 （安在開合處使人不能隨便打開的器具） lock 2 （姓氏） a surname Ⅱ動詞1 （上鎖） lock up 2 ...
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 間 : 間Ⅰ名詞1 （中間） between; among 2 （一定的空間或時間里） with a definite time or space 3 （一間...
  • 時間 : time; hour; 北京時間十九點整19 hours beijing time; 上課時間school hours; 時間與空間 time and spac...
  1. Full quanta theory was used in analysis the working principle of laser, educed the photon states of single pattern radiate in two energy - step system, and simulated the establishment of laser mode and statistical distribute of photon. according to elf consistent equations of rlg ; build the simulated program with labwindows / cvi and do some simulation experiments, the result of simulation matched the theory perfect perfectly and conform to the experiments, the locked - in and pattern competition coursed the periodic light intensity

    在激光陀螺自洽場方程組的基礎上，運用labwindows / cvi軟體建立了靈活方便的激光陀螺模擬平臺，並進行模擬試驗，模擬試驗結果與理論分析很好的相符合，且能夠較好地說明陀螺試驗現象，即在閉鎖閾值附近，由於閉鎖效應和模競爭相互影響，使得激光腔中兩行波相互關聯，光強差隨時間呈周期性變化。
  2. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面積是電路設計要考慮的主要因素，不同的電路形式具有不同的優缺點，如cmos互補邏輯電路功耗低，面積小，速度相對較慢； scfl （源極耦合fet邏輯）電路速度高，功耗和面積較大。所以要針對具體設計需要選用適當的電路形式或其組合結構，以滿足設計要求。觸發器是分接器的基本組成單元，建立時間和保持時間是影響電路速度的關鍵，所以減小建立時間和保持時間是觸發器設計的主要目標，本文著重介紹了scfl鎖存器的設計和優化方法。
  3. Pessimistic concurrency is not a scalable option when users are interacting with data and causing records to be locked for relatively large periods of time

    如果用戶與數據進行交互，會使記錄鎖定相對長的時間，保守式並發並不是可伸縮的選項。
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