塊邏輯設計 的英文怎麼說

中文拼音 [kuāiluóshèjì]
塊邏輯設計 英文
block logic design
  • 塊 : 名詞（古時佩帶的玉器） penannular jade ring （worn as an ornament in ancient china）
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 設 : Ⅰ動詞1 （設立; 布置） set up; establish; found 2 （籌劃） work out : 設計陷害 plot a frame up; fr...
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 邏輯 : logic
  • 設計 : devise; project; plan; design; excogitation; layout; layout work; styling
  1. At the same time, it also illustrates the superiority of this kind of communication by introducing the profibus field bus. take the transformation of focke packaging machine as an example, the main content is as follows : 1st, to analyze the plc control system of s5 series, and determine the concrete functions that the new plc control system hopes to achieve as well as how to achieve the goal through studying the work program of the original one ; 2nd, to demonstrate the advantage of the field bus in the process of digital alternation by introducing the principle agreement of field bus profibus ; 3rd, to achieve each function of the original control system through using siemens ' s plc control system in the design of hardware and step 7 in the software as well as designing and compiling control system of focke packaging machine ; 4th, to use fm455 for controlling temperature not only can meet the system ’ s severe request for temperature and efficiently avoid many demerits of the temperature control instrument but also can bring convenience for operation and maintenance ; 5th, to use the intouch configuration software to compile monitor and control program can accomplish the goal for real - time surveillance and control of the production line, while setting some parameters can provide a powerful alarming function

    以改造focke包裝機為例，主要內容如下: 1 、通過熟悉原有控制系統的工作流程，分析了原s5系列可編程邏輯控制器的控制系統，確定新的可編程邏輯控制器控制系統需要實現的具體功能以及其實現方法; 2 、在本系統數據交互中，通過介紹profibus現場總線原理協議，論述了現場總線在工業通訊中的優點; 3 、下位機硬體設計上使用西門子可編程邏輯控制器控制系統，軟體平臺採用西門子step7 ，設計和編制了focke包裝機控制軟體，實現了原有控制系統的各項功能; 4 、本系統對溫度要求嚴格，採用溫控儀表控制溫度不能滿足系統要求，而且溫控儀表操作和維護都不方便，因此採用fm455溫度控制模塊進行溫度控制，滿足了系統對溫度的要求，同時又有效地避免了溫控儀表在操作和維護上的缺陷; 5 、在監控系統上，使用intouch組態軟體設計了系統的監控界面，從而實現了對生產線的實時監控，並且可以通過界面設置系統的一些參數，同時提供了較強大的報警功能。
  2. This paper has accomplished part work of it, include : the research on the behavior based control method, the visual technique of robot and the application of active vision on behavior based robot. the main work and innovative ideas include : on the base of technique analyze of behavior based robot, a behavior system structure of rira - robot behavior - based robot and a behavior coordinator by combine the fuzzy logic control with multiple objectives propriety - based decision have designed, the ability of competence in multiple behavior and no collision within the intercurrent behavior have enhanced

    本文完成了其部分內容的研究，包括：機器人基於行為控制方法和策略的探討，移動機器人視覺技術的分析研究，主動視覺在機器人行為控制技術中的應用等。本文的主要工作和創新點包括：在機器人行為控制技術分析的基礎上，設計了rira - robot基於行為機器人的模塊、分層式行為體系結構。通過基於模糊邏輯行為控制和基於優先級的多行為決策相結合的控制策略，設計了機器人行為協調器，增強了多行為競爭和並發行為無碰撞的能力。
  3. Primary policy of design is sorting and distilling logic function block ? lfb first, then choose the language of configuration and lfb development for msr

    設計的主要方針是首先分類和提取出邏輯功能模塊lfb ，接著選擇msr使用的配置及lfb開發語言。
  4. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  5. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  6. Nowadays, all functions of a calculator including calculating units, display driver, keyboard interface and so on, are integrated on one single chip

    現代計算器使用一塊集成電路晶元來完成各種運算、顯示驅動和鍵盤介面等完整功能，依賴的是高度集成的動態cmos邏輯和微碼設計技術。
  7. 3 ) the content of generator module design includes the design factor, design outline, software design and experimentation. the generator module must complete the analog signals calculating, and make an order for shutting off connected generators in the condition of generators settings, concatenated logics and switch signal input, then communicate with the decision module

    3 ）發電機模塊的設計內容包括設計考慮因素、設計要點、軟體設計以及實驗驗證等，模塊必須完成對接入的發電機機組模擬量的計算；在機組設置、連鎖邏輯和開入信息等條件下對接入的發電機機組排出一個切機順序；完成模塊間通信。
  8. It is divided into port state control ( psc ) security check, flag state control ( fsc ) security check, ships quality appraisal, assistant business, report forms, the assurance of the target ship, electronic declare management, parameter design and purview management, the form design. the course of system implement is given in the thesis. the thesis emphasized to introduce the business logic of the psc security check and report forms 。 the implementation of pagestudio is detailed in the thesis

    深圳海事數字平臺分為港口國安全檢查（ psc ） 、船艦國安全檢查（ fsc ） 、船舶質量評價、輔助業務、報表、目標船的確定、電子申報管理、參數設計與權限管理、表單設計器9個功能模塊，在文中給出了系統開發環境搭建過程，並著重介紹了psc安全檢查與報表統計模塊的業務邏輯。
  9. Each logic module was verified by simulation

    通過模擬，驗證了各個模塊邏輯設計的正確性。
  10. The system design includes information model, function design and dada - base logical relation. the information model is established by entity - relation method, and the e - r picture is ploted, and the in - out diagram is gived out ; the fuction designed is established by idef0 method, the subsystems are designed according to the model in detail, we give out the explaining document and explain the calculation method for the model ; we design the data - base logical relation by the above models, decide the distributing and partition the relation diagram of the data - base, then define the logical structure of the diagrams

    其中信息建模採用實體-聯系的方法建立系統的信息模型，並用idef1x圖表示出該信息模型，同時給出電泵物資管理系統輸入輸出信息表；功能設計用idef _ 0方法建立電泵物資管理系統分系統功能模型，參照功能模型對內部各子系統進行詳細設計，給出分系統功能模塊的詳細說明書及相應功能演算法描述；數據庫邏輯設計依據系統分析結果、信息模型及功能模型，確定電泵物資管理系統數據庫分佈，劃分數據庫內部關系表，定義表的具體邏輯結構。
  11. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。
  12. There are six sub - modules in it : single - chip unit, data transfer unit, parallel data transfer / receive unit, serial data transfer / receive unit, system reset management and system power unit. this paper studies the design and realization of net interface module, mainly discusses design of data transfer unit ' s logic and the improvement of single - chip unit ' s software

    論文首先從系統設計思想出發，對網路介面模塊的總體設計實現進行了研究，接著對作者主要研究的軟硬體分工協同設計中的軟體完善部分，邏輯設計部分，以及最後的邏輯測試、系統測試進行了重點論述。
  13. This paper deeply discusses the content and structure of process data, establishes a xml ( extensible markup language ) process data model, and presents the xml expression of the special process data. combined with the application of nanqi capp system, some disposal mechanism and methods are proposed on the basis of the xml data model, such as data exchange, data transport, data storage, data query, data security and data integration. at the end of this paper, the realization of several capp functional modules are expounded to interpret the disposal details of xml process data

    本文詳細論述了工藝數據的內容和結構，通過概念建模和邏輯設計建立了基於xml標準的工藝數據模型，給出了特殊工藝數據的表達方式和應用描述，在此基礎上結合企業b s模式capp系統的開發提出了針對xml工藝數據的一些處理機制和方法：數據轉換、數據傳輸、數據存儲、數據查詢、數據安全和數據集成等，並通過工藝統計和基本信息查詢兩項capp功能模塊的實現過程對此作了具體闡述。
  14. The vd is composed of four functional units : 1 ) the branch metrics unit ( bmu ) ; 2 ) the add - compare - select unit ( acs ) ; 3 ) the path metrics unit ( pmu ) ; 4 ) the survivor memory unit ( smu ) ; regarding the power dissipation of the viterbi decoder, the smu is the hottest spot in the viterbi decoder due to the frequent memory accesses. there are two traditional techniques for the realization of survivor memory unit in viterbi decoder - - register exchange ( re ) and trace back ( tb ) method

    這是當前開展低功耗邏輯優化的重要方面，也是本課題採用的方法。 viterbi譯碼器主要由四個功能單元組成:分支度量單元（ bmu ） ，加比選單元（ acs ） ，路徑度量存儲單元（ pmu ） ，倖存路徑存儲和輸出單元（ smu ） 。本文所做的viterbi譯碼器設計採用模塊化的設計方法，先對各個功能單元進行優化設計，然後將各個功能單元組合在一起，形成最終的譯碼器。
  15. Simulations are executed in altera ’ s quartus ii environment with altera ’ s stratix family fpgas using verilog hdl after analysis. the results show that the sfn adapter can properly insert mip into transport stream and the time to be delayed in sync system can be correctly calculated and carried out with fifo

    在對每一個模塊的設計要點做了詳細說明之後，採用verilog語言編寫各模塊邏輯代碼，在altera公司的quartusii5 . 0集成開發環境下，基於altera公司stratix系列fpga對各模塊及整個單頻網適配器進行了模擬。
  16. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
  17. A complete vvp instrument consists of one enhanced main board and several plug - in boards, which is suitable for constructing basic instruments ( no cpu ), typical instruments ( a single cpu ) and advanced instruments ( multi - dsp )

    本章詳細闡述了vvp平臺的設計思想、體系結構以及vvp控者模塊邏輯設計的實現。
  18. Secondly, the sub - function blocks of fft ( fast fourier transform ) are finished in max + plus ii software platform, and each of them has been designed carefully and simulated in the software

    然後用max + plus軟體平臺編程實現快速傅立葉變換的各個軟體模塊，並進行了大量的邏輯設計和軟體模擬。
  19. In the part of overall design, the functional model and seven sub - system structured charts are given, in which the functions of each model are defined and specific descriptions are given out for the overall and eight sub - system models. according to the specific situation of cac, client / sever mode is adopted for cac - hrmes. in database design, identification of database and supporting software of cac - hrmis are given, the logic and physical design of database is carried out

    在總體設計部分，本文給出了cac - hrmis功能模塊結構總圖以及7個子系統結構圖，規定了各個模塊的功能，同時對主控模塊以及子系統中8個模塊的設計進行了具體的說明；依據成飛公司的具體情況，將cac - hrmis的拓撲結構設計為客戶機服務器模式；在數據庫結構設計部分，依次給出了cac - hrmis數據庫的標志符、支持軟體，並進行了數據庫的邏輯設計和物理設計。
  20. According to the function of test platform, the test platform is partition into a few modules. those modules are designed with verilog hdl and the key problems are discussed in details. the verilog codes for transmit and receive end of test platform are simulated under quartus ii 5. 0 ise, and debugged by downloading the verilog programs into ep1s25f780c and ep1s80b956c6 developing kits

    在對每一個模塊的設計要點做了詳細說明之後，採用verilog語言編寫各模塊邏輯代碼，在altera公司的quartusii5 . 0集成開發環境下，基於altera公司stratix系列fpga對各模塊及整個窄帶ldpc解碼-誤碼測試平臺進行了模擬並將發端和收端的verilog程序分別下載到altera的ep1s25f780c和ep1s80b956c6開發實驗板進行調試。
分享友人
分享到 Line

分享到臉書