指令周期 的英文怎麼說

中文拼音 [zhǐlìngzhōuqī]
指令周期 英文
cycle, instruction
  • 指 : 指構詞成分。
  • 周 : Ⅰ名詞1 （圈子; 周圍） circumference; periphery; circuit 2 （星期） week 3 [電學] （周波的簡稱） c...
  • 期 : 期名詞[書面語]1. （一周年） a full year; anniversary 2. （一整月） a full month
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  1. As a result of studying, we gain three system time capability parameter of monolayer bus framework and two - double bus framework, data bus utilization, length of the data waiting queue and time of system timed, basing on fixed bc control seasonal repertoire timed petri net and stochastic petri net

    研究結果分別得出了單總線和雙總線的基於固定主控端周期指令時延petri網的數據總線利用率、等候消息隊長、系統延時時間；基於隨機petri網的數據總線利用率、等候消息隊長、系統延時時間共三個系統時間性能指標。
  2. The two steps are referred to as the fetch cycle and the execute cycle

    這兩個步驟被稱為取指令周期和執行周期。
  3. Instruction fetch cycle

    取指令周期
  4. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  5. The processing required for a single instruction is called an instruction cycle

    處理一條指令的過程稱為指令周期。
  6. At the beginning of each instruction cycle, the cpu fetches an instruction from memory

    在每一個指令周期的開始， cpu從內存中取一條指令。
  7. Using the simplified two - step description explained above, the instruction cycle is depicted in figure 2 - 3

    以上述最簡單的兩個步驟為例，指令周期如圖2 - 3 。
  8. On succeeding instruction cycles, it will fetch instruction from locations 301, 302, 303, and so on

    在隨后的指令周期里，它將依次從301 、 302 、 303地址單元取指令，依此類推。
  9. The aim of mips pipeline is that one instruction completed in one period averagely

    Mips流水線的設計目標是要達到平均每個時鐘周期完成一條指令，這就是流水線的極限速度。
  10. At the base of compiler forepart, considering repertoire, addressing mode and instruction period of object machine, adopting backfill to fill data for machine code in order to generate right object code, assemble language program

    在編譯前端的基礎上，考慮目標機的指令系統、尋址方式和指令周期，採用回填技術對機器碼填充數據以生成等價有效的目標代碼? ?匯編語言程序。
  11. There has to be some gap of clock cycles between the unblocking of signals and the next instruction carried by the process, and any occurrence of a signal in this window of time is lost

    從消除信號阻塞到進程執行下一個指令之間，必然會有時鐘周期間隙，任何在此時間窗口發生的信號都會丟掉。
  12. It aims at reducing the number of execution cycles of instructions, and has experienced from the period of single issue architecture to the period of multiple issue architecture. in the past twenty years, risc has become more and more mature abroad. it makes great sense to develop our own risc and it is a effective way to develop our own risc with the instruction set which is compatible with those of risc which has been widely used

    80年代初出現的risc技術是計算機體系結構的重大變革，它以減少指令執行的平均周期數為結構設計的主要目標，經歷了從單發射結構到多發射結構的演變過程，解決了深度流水技術、相關技術、轉移預測技術、編譯優化技術等一系列技術難點，在20多年的時間里， risc技術的發展已日趨成熟與完善微處理器在軍事和民用領域都有著廣泛的應用，研製具有我國自主獨立版權的微處理器在當今具有重大意義。
  13. The design team s goal was to complete one instruction per clock cycle, and to accommodate 300 calls per minute

    設計小組的目標是在每個時鐘周期內完成一條指令，從而每分鐘可以處理300個電話。
  14. Moreover, ck510 employs some low - power design techniques with performance improved. there are three instructions controlling power consumption on system - level and gated clock technique is widely used in ck510. integer computing ability is very important for embedded cpu

    在嵌入式處理器中，整數單元一般進行指令譯碼、指令發射和指令執行，是處理器中的一個重要部件，它直接影響著處理器的性能（ cpi ，每條指令花費的時鐘周期）和功耗指標。
  15. The main works were listed below : 1. as the core of image tracker, the advanced dsp technology ( adsp - ts201 ) and the programmable logic device ( ep1s40f1020 chip ) were combined together to make certain that instruction was completed within single instruction period

    主要體現在下面幾點: 1 .圖像跟蹤器的硬體平臺以先進的dsp技術（ adsp - ts201 ）和可編程邏輯器件（ stratix系列的ep1s40f1020晶元）為核心，構成實時的圖像跟蹤處理器，使得指令可在單指令周期內完成運算。
  16. Based on analysis, we finished the architecture design and the division of the functional modules. allowing for the pic16c57 mcu can not suit the high speed situation, we improving the clock structure through using one clock instead of the original four clock technology. cooperating the instruction work step, the new clock structure executed one clock cycle per instruction

    針對pic16c5x系列微控制器不能適用於高速場合的需要，對其時序結構進行了改進設計，用單時鐘代替原來的四相時鐘技術，採用二級流水結構，配合指令的工作節拍，使指令執行周期縮短為單個時鐘周期。
  17. Ipc instructions per clock cycle

    指令時鐘周期
  18. Single - cycle bit permutations with momr execution

    利用momr執行完成單指令周期位置換
  19. Dsp owns rapid instruction periods, address buses separated from data buses, which can excellently adapt to the rapid digital signal process

    Dsp擁有快速的指令周期以及地址、數據總線分離等適合快速數字信號處理的優點。
  20. However, stam method significantly reduces hardware resource taken up by the lookup table, and need not to execute iteratively. and it can rapidly fulfill one time computation in an instruction period

    而stam方法極大的減小了查表法佔用的硬體資源，而且不必循環執行，可以在一個指令周期內完成一次計算任務，運算速度快。
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