指令地址 的英文怎麼說

中文拼音 [zhǐlìngdezhǐ]
指令地址 英文
address instruction
  • : 指構詞成分。
  • : 名詞(建築物的位置; 地基) location; site; ground; foundation
  • 指令 : 1 (指示; 命令) instruct; order; direct2 (上級機關對下級機關的指示) instructions; order; direc...
  1. If we load this known address, as data, into the program counter, we execute a jump instruction.

    如果我們將已知的依數據加載到程序計數器中,就可以執行一條轉移
  2. Addressless instruction format

    格式
  3. Each location contains a binary number that can be interpreted as either an instruction or data

    每一個單元包含一個二進制數,該數既可以被解釋為也可以是數據。
  4. Code instructions address data using the virtual address ; the memory management unit ( mmu ) is responsible for the translation of the virtual address to the physical ram address

    代碼使用了虛擬的;內存管理單元( mmu )負責把虛轉換成實際的物理ram
  5. The addr2line tool which is part of the standard gnu binutils is a utility that translates an instruction address and an executable image into a filename, function name, and source line number

    Addr2line工具(它是標準的gnu binutils中的一部分)是一個可以將和可執行映像轉換成文件名、函數名和源代碼行數的工具。
  6. System calls. when an emulator ordinarily encounters a powerpc system call instruction, it emulates the exception by storing the instruction address into the srr0 register, setting some architecture - defined bits in srr1, and transferring control to physical address 0xc00. some powerpc variants allow more control over this behavior, but this is the traditional powerpc model

    當模擬器正常碰到一個powerpc系統調用時,它便將指令地址存入到srr0寄存器,設置srr1中某些體系結構定義的位,並將控制權轉交給物理0xc00 ,從而模擬這個異常(有些powerpc的變種允許對這種行為有更多的控制,但是這里的這種是傳統的powerpc模型) 。
  7. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點,闡述了eda技術和asic設計的主要流程,闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理,虛擬指令地址的結構和產生, mmu結構,包括tlb結構和虛擬指令地址向物理指令地址的生成流程, cache結構,尋原理和的寫策略,高速緩存的尋原理和結構,以及的獲取流程。
  8. On succeeding instruction cycles, it will fetch instruction from locations 301, 302, 303, and so on

    在隨后的周期里,它將依次從301 、 302 、 303單元取,依此類推。
  9. Branch instructions using the contents of the link register or count register to specify the branch target address

    使用鏈接寄存器或計數寄存器來定轉移目標的轉移
  10. The ability to save the address of the next sequential instruction is provided on all branch instructions, including the branch to link register instruction

    所有的轉移都具備保存后繼順序指令地址的能力,包括到鏈接寄存器的轉移。
  11. The current block is the code containing the current location, instruction pointer address

    當前塊是包含當前位置()的代碼。
  12. Which executes instructions from the current instruction pointer address printing the instruction on the screen until it encounters an instruction that would cause a branch

    ,它執行從當前開始的(在屏幕上列印) ,直到它遇到將引起分支轉移的為止。
  13. As the april 2002 column explained, expect comes closer than any other language to being universal for the sorts of needs system programmers are likely to have with their servers

    關于s / / /替換命,還有其它幾件要了解的事。首先,它是一個命,並且只是一個命,在所有上例中都沒有
  14. Instruction the alignment of the address may not be to a 4 - byte boundary

    的對可以不是對於4位元組邊界的。
  15. I ve found it exhiliratingly useful to be able to supervise server statuses and display them for others from any location with a web browser

    如果不為該命,那麼它將應用到每一行,並產生如下的輸出:
  16. Address instruction, functional

    函數指令地址
  17. Address instruction, immediate

    實時指令地址
  18. Address source, instruction

    指令地址
  19. A register in the processor that contains the address of the next instruction to be executed. also known as a program counter

    包含下一條要執行指令地址的處理器中的寄存器。也叫程序計數器。
  20. Of bytes starting at the specified address of type

    將以(類型為
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