指令結構 的英文怎麼說

中文拼音 [zhǐlìngjiēgòu]
指令結構 英文
command structure
  • 指 : 指構詞成分。
  • 結 : 結動詞（長出果實或種子） bear （fruit）; form （seed）
  • 構 : Ⅰ動詞1 （構造; 組合） construct; form; compose 2 （結成） fabricate; make up 3 （建造; 架屋） bui...
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  • 結構 : 1 （各組成部分的搭配形式） structure; composition; construction; formation; constitution; fabric;...
  1. The procedure functions in the compare between partial image of dynamic collection and corresponding image of the airscape. in chapter 5, basing on the analysis of correlative theory of digital image, we introduce the improved fasted - down algorithm and simulative anneal algorithm, which applies to nn calculation, an d bring forward the unique and effective means, correlative original value evaluation. basing on the combination of correlative arithmetic, a stable, high - speed and exact correlative arithmetic is formed, which makes it possible to apply computer vision detection of single - needle quilting in industrial production

    本文展開研究並取得一定成效：構建了基於pci總線的微機實時圖像採集系統；在採集的布料總圖（鳥瞰圖）的基礎上，通過數字圖像的數字濾波、圖像增強、邊緣檢測等處理，提取布料圖像的邊緣，對輪廓的矢量化的象素點進行搜索，得到相應的圖案矢量圖，從而確定絎縫的加工軌跡，生成加工指令；在進給加工過程中，主計算機對動態局部圖像與總圖（鳥瞰圖）的對應部分進行圖像相關的匹配計算，應用數字圖像理論，結合神經網路計算的改進最速下降法和模擬退火演算法，提出獨特而有效的相關迭代初始值賦值方法，形成穩定、高速和準確的相關運算，實現單針絎縫視覺測量和自動控制。
  2. Cisc : complex instruction set computing

    復雜指令結構
  3. Risc : reduced instruction set computing

    精簡指令結構，是相對于
  4. Following this hypothesis, this study first investigated the topologies of the vowel system across the motor, kinematic, and acoustic spaces by means of a model simulation, and then examined the linkage between vowel production and perception in terms of a transformed auditory feedback experiment

    為了獲得切實的證據，我們首先藉助于模型模擬來探索母音體系的拓撲結構在運動指令空間，運動學調音空間，聲學空間的表象，接著通過變形聽覺反饋實驗來檢驗母音生成和感知之間的關聯。
  5. Jx5 is a complex microprocessor, which contains cache, microcode rom, instruction prefetch unit, instruction decode unit, integer unit, mmx unit, floating point unit, page unit, bus unit, dp logic, apic and so on. it is very difficulty to test a such complicated microprocessor and receive anticipative fault coverage ratio. so, we must add dft in cpu ’ design

    Jx5微處理器是一款結構異常復雜的微處理器，它的內部包含有: cache 、微碼rom 、指令預取部件和動態分支預測部件、指令譯碼部件、整數部件、多媒體部件、浮點部件、分段和分頁部件、總線介面部件、雙處理器介面部件、可編程中斷控制部件等。
  6. In the logic design, the fundamentals and characteristics of ieee std. 1149. 1 specification and usb protocol are introduced first of all. according to altera ’ s fpga cyclone, it analyzes the architecture and jtag instructions of boundary scan test ( bst ). then the dissertation analyzes how to program cyclone device and offer the scheme of the design which is realized in verilog hdl by modelsim and quartus ii software

    在介面邏輯設計中，首先分析ieee1149 . 1標準和usb協議，理解邊界掃描測試和usb數據傳輸的工作方式，然後針對altera公司的fpga器件cyclone ，通過分析它的邊界掃描測試結構和各種jtag指令，研究它的編程過程和編程特點，並提出設計方案。
  7. The crucial trait of risc architecture is that it can fit the pipeline compatibly

    Risc體系結構的重要特點是其便於利用流水線結構進行指令操作。
  8. At the same time the author emphasizes that by no means can the teaching mode violate the usual principles, such as syllabus and curriculum standard, teaching contents, step - by - step instruction, and suiting the instruction to the students " level. simultaneously the focal points are also the new ideas that the author put forward in the dissertation since they constitute the crux in improving the students " reading comprehension ability through the combination of discourse analysis theories and classroom english teaching. after presenting and analyzing the results and data, the author argues that the adopted theories prove to be fruitful in enhancing students " reading comprehension ability, and states their far - reaching

    實驗完成後通過分析數據和結果，筆者得出令人信服的結論，即語篇分析理論對高中閱讀教學具有重要的指導和啟發意義，以它們為指導的教學模式明顯優于傳統的閱讀教學方法，並提出了實驗對今後閱讀教學的幾點啟示：加強對語篇宏觀結構的分析、注重知識面的拓展，掌握各種常見的閱讀技巧和策略、重視銜接手段的教學和訓練以及慎重選材和科學設問。
  9. It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc

    它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成，以流水和超標量方式執行指令，指令集和介面時序兼容powerpc ，是典型的risc微處理器結構。
  10. Risc processors generally feature fixed - length instructions, a load - store memory architecture, and a large number of general - purpose registers and / or register windows

    Risc處理器一般的特徵是固定長度的指令集，一個負載儲備存儲結構，和大量通用寄存器，及寄存器窗口。
  11. The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block

    設計的riscmcu採用14位字長指令總線和8位字長數據總線分離的harvard結構和二級指令流水設計，並使用硬布線邏輯代替微程序控制，加快了微控制器的速度，提高了指令執行效率。
  12. The core is based on harvard architecture with 16 - bit instruction length and 8 - bit data length. the performance of mcu has been improved greatly by introducing single - clock - cycle instructions, setting multiple high - speed working registers and replacing micro - program with direct logic block etc. to keep the mcu core reusable and transplantable, the whole mcu core has been coded for synthesis in verilog hdl

    該mcu核採用哈佛結構、 16位指令字長和8位數據字長，通過設計單周期指令、在內部設置多個快速寄存器及採用硬布線邏輯代替微程序控制的方法，加快了微處理器的速度，提高了指令的執行效率。
  13. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  14. On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology

    本文在分析sparc指令系統的基礎上，研究了流水技術及其相關問題的解決方法，並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、數據相關和轉移相關的問題。
  15. This paper discusses msu ' s design, implementation and verification, implements the integration of the " longtengrl " system and studies the optimization of instruction cache

    本課題組設計的「龍騰r1 」微處理器晶元，指令系統與motorola公司的powerpc603e兼容，體系結構自主設計。
  16. System calls. when an emulator ordinarily encounters a powerpc system call instruction, it emulates the exception by storing the instruction address into the srr0 register, setting some architecture - defined bits in srr1, and transferring control to physical address 0xc00. some powerpc variants allow more control over this behavior, but this is the traditional powerpc model

    當模擬器正常地碰到一個powerpc系統調用指令時，它便將指令地址存入到srr0寄存器，設置srr1中某些體系結構定義的位，並將控制權轉交給物理地址0xc00 ，從而模擬這個異常（有些powerpc的變種允許對這種行為有更多的控制，但是這里的這種是傳統的powerpc模型） 。
  17. The paper elaborates risc technology characteristic and 5 - stage pipeline architecture and function of the 64 - bit risc cpu, and dwells on 64 - bit vega cpu characteristic, and details the eda technology and the main flow of asic design, and elaborates the operation and exception process of the vega cpu and virtual instruction address " architecture and generation, and details cache architecture and mmu. the master dissertation dwells on virtual address translating into physical address, instruction cache finding address and instruction fetching, too

    詳細的闡述了64位vegacpu的特點，闡述了eda技術和asic設計的主要流程，闡述了vegacpu流水線結構、流水線操作、流水線暫停和異常處理，虛擬指令地址的結構和產生， mmu結構，包括指令tlb結構和虛擬指令地址向物理指令地址的生成流程， cache結構，尋址原理和指令的寫策略，指令高速緩存的尋址原理和結構，以及指令的獲取流程。
  18. Superscalar risc microprocessor is the further development of reduced instruction set computer, it improve the instruction - level - parallism by means of adding parallel pipelining function units and dynamic on - chip scheduling. this thesis anslysises the architecture and the diversified techniques of superscalar computer

    超標量risc微處理器是精簡指令結構（ risc ）的進一步發展，它通過增加并行流水執行單元並結合片上硬體動態調度來提高指令并行度。
  19. Pulse compression performances of many pulse compression signals are analyzed in frequency domain. and the methods to design kinds ok range sidelobe suppression filters are proposed. this dissertation produced the method to improve parallelism of fft calculation in vliw architecture and a pulse compression procession system in frequency domain based on adsp2106x which had been emulated by using visualdsp + +, and the result is meet the theory

    本文主要介紹了使用越來越廣泛的頻域數字脈壓處理技術，分析了各種脈壓信號的頻域脈壓性能及其旁瓣抑制濾波器設計，設計了一個基於adsp2106x晶元的頻域數字脈壓處理系統，針對adsp2106x晶元的vliw指令結構，利用晶元的并行運算能力提高fft效率，並使用visualdsp + +對系統進行了模擬測試，結果與理論相符。
  20. Isa is divided into three parts according to the design consideration of md32. rich addressing and operation modes are supported in md32 isa. risc / dsp pipeline partition rules are given based on the relations between instruction set and data path design

    在md32設計中採用了具有自身特色的設計方法，探索出一套面向risc dsp指令結構的微結構設計原則和方法，如并行設計、內部流水設計、集中控制等。
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