指令體系結構 的英文怎麼說

中文拼音 [zhǐlìngtǐxìjiēgòu]
指令體系結構 英文
instruction architecture
  • 指 : 指構詞成分。
  • 體 : 體構詞成分。
  • 系 : 系動詞（打結; 扣） tie; fasten; do up; button up
  • 結 : 結動詞（長出果實或種子） bear （fruit）; form （seed）
  • 構 : Ⅰ動詞1 （構造; 組合） construct; form; compose 2 （結成） fabricate; make up 3 （建造; 架屋） bui...
  • 指令 : 1 （指示; 命令） instruct; order; direct2 （上級機關對下級機關的指示） instructions; order; direc...
  • 結構 : 1 （各組成部分的搭配形式） structure; composition; construction; formation; constitution; fabric;...
  1. The crucial trait of risc architecture is that it can fit the pipeline compatibly

    Risc體系結構的重要特點是其便於利用流水線結構進行指令操作。
  2. This paper discusses msu ' s design, implementation and verification, implements the integration of the " longtengrl " system and studies the optimization of instruction cache

    本課題組設計的「龍騰r1 」微處理器晶元，指令系統與motorola公司的powerpc603e兼容，體系結構自主設計。
  3. System calls. when an emulator ordinarily encounters a powerpc system call instruction, it emulates the exception by storing the instruction address into the srr0 register, setting some architecture - defined bits in srr1, and transferring control to physical address 0xc00. some powerpc variants allow more control over this behavior, but this is the traditional powerpc model

    當模擬器正常地碰到一個powerpc系統調用指令時，它便將指令地址存入到srr0寄存器，設置srr1中某些體系結構定義的位，並將控制權轉交給物理地址0xc00 ，從而模擬這個異常（有些powerpc的變種允許對這種行為有更多的控制，但是這里的這種是傳統的powerpc模型） 。
  4. Once these changes ( dual mode, privileged instructions, memory protection, timer interrupt ) have been made to the basic computer architecture, it is possible to write a correct operating system

    一旦對一個基本的計算機體系結構完成了以上修改（雙模式、特許指令、內存保護、定時器中斷） ，就有可能寫出正確的操作系統。
  5. Then the thesis presents two peephole optimizations for the c 、 c + + compiler based on the architecture of thump to improve the quality of generated codes. one optimization is on multimedia applications. since thump supports two mmx instructions, the optimized compiler can generate these instructions to improve the performance

    論文討論了如何利用thump體系結構的特點進一步提高目標代碼生成質量的優化技術，並實現了兩種窺孔優化，包括針對thump的多媒體指令的優化演算法和基於thump的高速乘除處理部件的優化演算法。
  6. The powerpc architecture contains cache management instructions for both application - level cache accesses

    Powerpc體系結構包含了面向應用級高速緩存訪問的高速緩存管理指令。
  7. Finally, studies the instruction system of cos upon a dedicated instruction of smartcos - xc. chapter 4 discusses the smartcos - xc and gives the design and implementing of a smart card file system framework. based on this, this paper gives a simulation of head - end encryption of entitlement control message ( ecm ) and entitlement management message ( emm ), and implements the decryption of ecm and emm in the smart card

    在對通用cos的研究的基礎上，首先簡單分析了smartcos - xc ，結合該cos ，論文針對有條件接收系統，按不同用途、不同類型分別設計並實現了存儲用戶授權及智能卡應用的文件體系結構，通過該cos的指令系統，設計並實現了模擬前端授權控制信息（ entitlementcontrolmessage ， ecm ） 、授權管理信息（ entitlementmanagementmessage ， emm ）數據生成模塊及用戶端ecm 、 emm解密模塊。
  8. Design the data path of the risc 51 ip core. emphasis on the arithmetic logical unit ; 3. design the control path of the risc 51 ip core to make the risc 51 ip core ' s instruction set compatible with mcs51 microcontroller ; 4

    （ 3 ）設計risc51ipcore控制通路，實現risc51ipcore內部指令與原mcs51指令系統的完全兼容，具體設計原mcs51指令與risc結構51核指令的轉換過程，及正確的指令時序。
  9. This architecture became known as risc reduced instruction set computer

    這種體系結構稱為risc （精簡指令集計算機） 。
  10. The verification process for a digital signal processor with very long instruction word ( vliw ) named thuasdsp2004, which is developed by tsinghua university microelectronic institute sponsored by national natural science foundation, is analyzed at the register - transfer level in this paper

    本文介紹在國家自然科學基金的資助下，由清華大學微電子研究所設計的具有超長指令字（ verylonginstructionword ， vliw ）體系結構特點的數字信號處理器thuasdsp2004的rtl級功能驗證工作。
  11. There are no push or pop instructions and no dedicated stack pointer register defined by the architecture

    體系結構沒有定義壓入或者彈出指令，也沒有定義專門的棧指針寄存器。
  12. It aims at reducing the number of execution cycles of instructions, and has experienced from the period of single issue architecture to the period of multiple issue architecture. in the past twenty years, risc has become more and more mature abroad. it makes great sense to develop our own risc and it is a effective way to develop our own risc with the instruction set which is compatible with those of risc which has been widely used

    80年代初出現的risc技術是計算機體系結構的重大變革，它以減少指令執行的平均周期數為結構設計的主要目標，經歷了從單發射結構到多發射結構的演變過程，解決了深度流水技術、相關技術、轉移預測技術、編譯優化技術等一系列技術難點，在20多年的時間里， risc技術的發展已日趨成熟與完善微處理器在軍事和民用領域都有著廣泛的應用，研製具有我國自主獨立版權的微處理器在當今具有重大意義。
  13. This thesis mainly focuses on the multi - level parallelism development and performance optimization of scientific programs on this architecture, and our works are summarized as follows. ( 1 ) we put forward the multi - level parallel computing time model, which is suitable for smp cluster to analyze program performance from the micro - aspect. we also provide a multi - level parallel optimization speedup model based on the single - processor speedup factor, which can evaluate program performance from three parallel levels and guide us to improve the programs

    本文圍繞這種多級并行體系結構中的超節點級、節點級和單機指令級三個層次的并行性開發與優化，在科學計算程序的綜合優化技術研究方面做了以下的工作與創新: （ 1 ）針對smp集群體系結構提出了多級并行計算時間模型，用於程序性能的微觀分析;將單機處理速度與加速比統一起來，提出了基於單機優化加速因子的多級并行優化加速比評價模型，該模型分別從三個并行層次的角度出發對程序性能進行評價，並指導對程序的改進與優化。
  14. A bus shared heterogeneous architecture consisting of one or more instruction set processor cores, one or more dedicated hardware ip cores and one or more on - chip memories usually provides a good solution

    基於總線互連的由一個或多個指令集處理器核、一個或多個專用硬體ip核、一片或多片片上存儲器構成的異質體系結構成為媒體系統晶元的合理選擇。
  15. This paper presents the yh ts - 1 instruction architecture, which based on the vector expansion of arm v4 instruction architecture. it supports vector processing and scalar processing in the same instruction set

    本文提出了基於armv4指令集體系結構擴展的銀河ts - 1指令集體系結構，在同一個指令集內同時支持標量機制和向量機制。
  16. The micro - kernel architecture is suitable for dual - core environment, because the micro - kernel architecture has a good module and its size is small. based on the analysis the source code and the dual - core hardware architecture, modify the module in order to suit for the dual instruction stream environment of the dual - core processor

    在對代碼分析的基礎上，總結出代碼中所體現出現的內核各模塊的內部結構，再結合雙核處理器的硬體特點，對模塊進行修改，相當于對模塊作加法運算，使其滿足雙核處理器的雙指令流體系結構。
  17. The digital signal processor becomes the preferred utility for realizing digital arithmetic rapidly and precisely relying on its particular hardware and instruction architecture

    而dsp （數字信號處理器）以其特有的硬體體系結構和指令體系成為快速精確實現數字信號處理演算法的首選工具。
  18. This paper analyze the architecture of amex86 microprocessor, including the analyzer of instruction system, addressing mode, scheduling and clock of instruction, the integration and validation of amex86 architecture. this paper mainly discusses the design and realization of data path and instruction decoder in detail

    本論文將對amex86體系結構的微處理器進行體系結構分析，包括指令系統的分析、尋址方式的分析，指令時序以及指令時鐘拍數的分析和amex86系統的集成及驗證等。
  19. They could be partitioned two sorts by structured computer organization. one is complex instruction set computer ( cisc ), another is reduced instruction set computer ( risc )

    Cpu的分類方法很多，最為典型的是按照體系結構把它們分為復雜指令集處理器（ cisc ）和精簡指令集處理器（ risc ） 。
  20. A novel 32 bit embedded fix - point superscalar risc core is developed. then we analysis the power dissipation of risc core from view of instruction - set - architecture, datapath, supply voltage and dynamic power optimization

    並從系統層次對risc處理器進行功耗分析，分別從改進指令體系結構、處理器數據通路、降低系統工作電壓和動態降低功耗四個方面進行低功耗研究。
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