數字邏輯實驗 的英文怎麼說

中文拼音 [shǔzìluóshíyàn]
數字邏輯實驗 英文
numerical logic experiments
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 實 : Ⅰ形容詞1 （內部完全填滿 沒有空隙） solid 2 （真實; 實在） true; real; honest Ⅱ名詞1 （實際; 事實...
  • 驗 : 動詞1. （察看; 查考） examine; check; test 2. （產生預期的效果） prove effective; produce the expected result
  • 數字 : 1. （表示數目的文字; 表示數目的符號） figure; digit; numeral; character; numeric character 2. （數量） quantity; amount
  • 邏輯 : logic
  1. Utilize advanced on - the - spot sensing technology, information digitization gathering technology, electromechanics integrated technology and computer logic analysis technology, carry on fault analysis and diagnose to power machinery in the operation state, provide the theoretical foundation and experimental data for power machinery designing at the same time

    利用先進的現場傳感技術、信息數字化採集技術、機電一體化技術及計算機邏輯分析處理技術，對運行狀態中的動力機械進行故障分析、診斷，同時為動力機械設計提供理論依據和實驗數據。
  2. The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance

    模擬實驗結果證明了改進演化演算法對于實現函數級數字組合邏輯電路的硬體演化是可行的，並且提高了演化演算法的演化效率和收斂性能。
  3. By exploring the characters of dynamic power supply currents of digital circuits using spice, this paper analyzed the relation between iddt and the switching activities when a circuit changes from one logical state to another

    本文通過spice實驗研究數字電路動態電流的特性，分析了數字電路的動態電流與電路邏輯狀態轉變之間的關系。
  4. Eda simulation and digital logical design and experiment

    模擬與數字邏輯設計實驗技術
  5. Thirdly, the paper researchs the application of single electron transistor and the synthesis theory of cicuit based on quantum dot cellular automata by synthesis example of quantum cellular neural network based on build schr ? dinger equation of coupling quantum dot. at last, the paper researchs digital integrated circuit design based on quantum dot cellular automata and design a 8 - bit quantum dot cellular adder by qcadsign based on a method of majority logic reducetion for quantum cellular automata, it prove this designer of 8 - bit quantum dot cellular adder is correctly

    Dinger ）方程為基礎的量子點細胞自動機電路綜合理論，本文以量子細胞神經網路為綜合實例，建立耦合量子點的薛定鄂（ schr ? dinger ）方程組，通過化簡得到類似細胞神經網路的非線性電路方程。最後研究了基於量子點細胞自動機數字集成電路設計，通過建立邏輯方程，簡化邏輯方程，並設計基於精簡qca擇多邏輯門8位加法器，並用qcadesign進行了模擬，實驗證明設計正確性。
  6. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  7. This course consists of lectures and labs on digital logic, flipflops, pals, counters, timing, synchronization, finite - state machines, and microprogrammed systems

    本課包括了數字邏輯、觸發器、 pal （可編程邏輯陣列） 、計數器、時序、同步、有限狀態機、和微控制系統方面的講課與實驗。
  8. According to the basic theory of iir filters, a scheme of hardware implementation is worked out combining with the fact that coefficients of numerator and denominator of transfer function are fixed and the structural feature of selected hdpld. from the clew of implementing a stratified ， modularized and parameterized design ， the thesis describes the hardware implementation of the iir filter with vhdl and schematic diagram design method. two examples that are iir notch filter and iir low - pass filter are given ， the stability of filters and the effects of quantification of coefficient are also analyzed

    以iir數字濾波器的基本理論為依據，結合濾波器的傳遞函數分子、分母系數固定這一事實和選用的高密度可編程邏輯器件的特點，確定了iir數字濾波器的硬體實現方案；按照層次化、模塊化、參數化的設計思路，採用vhdl硬體描述語言和原理圖兩種設計技術進行了iir濾波器的硬體設計；本文給出了iir陷波濾波器和低通濾波器兩個設計實例，對設計的濾波器都進行了穩定性分析和系數量化影響分析；最終將完成的iir濾波器的硬體設計配置到晶元中，並在製作的實驗電路中進行了實際濾波效果測試。
  9. Using bzl logic, security, anonymity and tracing ability of the digital - cash is verified. the protocol proves strong by using the factual system and being verified by the bzl logic

    通過在電子交易系統的實際應用和bzl邏輯的形式化驗證，證明了提出的數字現金協議是一個強壯的協議。
  10. In the field of verifying digital - cash, no good logic model describing and verifying a digital cash protocol has been brought forward either abroad or at home. in this background, the contents and purpose of my researches are to design a secure digital - cash protocol, devising a simple e - dealing system and building a logic model

    數字現金安全分析方面國內外都沒有一個能夠嚴格描述和驗證數字現金協議的邏輯模型，基於這種背景，本課題的研究目的是設計一個安全的數字現金協議，實現一個簡易電子交易系統來展示該協議的思想，並建立一個邏輯模型來形式化描述該協議且對其進行安全性分析。
  11. To achieve tuning the gain of the controller by software and digital logical circuits, this article took the first method for example and introduced the tuning process and tuning result in detail, meanwhile, it has also been validated by the experiments and matlab

    一種是通過計算機軟體對控制器增益進行調節，另?種是運用數字邏輯電路來調節增益，以第一種方法為例，詳細的介紹了調節過程、調節結果，並用實驗和計算機模擬加以驗證。
  12. In this thesis, we would present theory research and its implementation about mpeg - 2 ts stream “ health ” check analyzer. a brief narration about the background of our research and its mean would be put in the beginning. and then we would analyze structure of ts stream and its definition in iso / iec 13818 - 1, data structure of system layer and mechanism of decode would be stressed in this section, later, we would introduce principles and methods of mal - function check in mpeg - 2 ts network, parameters being presented by etsi tr 101 290 would be emphasized in this part

    本文將對mpeg - 2ts碼流「健康」檢測儀的理論研究和數字電路設計作出如下介紹:本課題研究的時代背景及研究現狀和意義; mpeg - 2ts碼流的數據結構，在iso / iec13818 - 1中的定義和描述，其系統層的數據結構及解碼機理; mpeg - 2ts碼流在網路中故障檢測的原理和方法， etsitr101290規定檢測參數分類; mpeg - 2ts碼流「健康」檢測儀實現的總體方案，基於fpga的數字邏輯電路實現方案總體模塊劃分，模塊劃分的依據，模塊實現功能;總體方案的具體實現，幾個重要參數如pcr間隔及精度檢測，快速crc檢測等的實現;設計實現的驗證方法，典型參數檢測實現的驗證模型及驗證結果。
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