數據流指令 的英文怎麼說

中文拼音 [shǔliúzhǐlìng]
數據流指令 英文
data flow instruction
  • : 數副詞(屢次) frequently; repeatedly
  • : 據Ⅰ動詞1 (占據) occupy; seize 2 (憑借; 依靠) rely on; depend on Ⅱ介詞(按照; 依據) according...
  • : Ⅰ動1 (液體移動; 流動) flow 2 (移動不定) drift; move; wander 3 (流傳; 傳播) spread 4 (向壞...
  • : 指構詞成分。
  • 數據 : data; record; information
  • 指令 : 1 (指示; 命令) instruct; order; direct2 (上級機關對下級機關的指示) instructions; order; direc...
  1. Making use of the packet data service and short data service of tetra, the mcs system enables front - line officers to use their portable radios and in - vehicle mobile data terminals mdts to exchange data messages with rcccs

    動電腦信息系統利用地面集群無線電的封包服務和簡短服務,前線警務人員可以使用手提無線電通訊機和車上的終端機與總區揮及控制中心交換信息。
  2. There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way

    Powerpc603e微處理器系統由定點執行單元、浮點單元、) cache 、總線介面單元、存儲管理單元組成,以水和超標量方式執行
  3. The risc mcu core is based on harvard architecture with 14 - bit instruction length and 8 - bit data length and two - level instruction pipeline the performance of the risc mcu has been improved by replacing micro - program with direct logic block

    設計的riscmcu採用14位字長總線和8位字長總線分離的harvard結構和二級水設計,並使用硬布線邏輯代替微程序控制,加快了微控制器的速度,提高了執行效率。
  4. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 ( sparcv8 )的結構,針對嵌入式應用具有以下特點:採用分離的cache (哈佛結構) ,五級水,硬體乘法器和除法器,中斷控制器, 16位的i / o埠和靈活的內存控制器,具有較強的異常處理功能,新模塊可以輕松的通過片上的ambaahb / apb總線添加。
  5. On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology

    本文在分析sparc系統的基礎上,研究了水技術及其相關問題的解決方法,並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、相關和轉移相關的問題。
  6. It includes : dynamic show of technics flow, real time data acquirement and show, history data save and print, fault alarm, etc. the plc control system mainly accomplishes the wastewater technics flow control, harmonizes the logical relationship among local intelligent control instruments and transmits the state of each local equipment to the industrial computer simultaneously, the plc control station receives the control commands from the industrial computer ; the local intelligent units take charge of the correlated parameters measure, disposal and control, and it will transmit the related parameters to the computer, etc. in this thesis, introduced municipal wastewater treatment technics, the integrated application program development of computer, the design method of plc control station, the communication between plc control system and computer, and the network of wastewater treatment with profibus - dp was also discussed

    上位計算機主要實現遠程監測和管理功能,具體包括:工藝程動態顯示、實時獲得及顯示、歷史存儲與列印、故障報警等功能plc控制系統主要完成工藝程式控制制以及協調現場各智能儀表之間的邏輯關系,將現場各設備的運行狀態通過通訊網路傳輸到上位計算機,並接收上位計算機的控制;現場各智能儀表單元負責各相關參的監測和處理、控制,並將有關參送往上位監控計算機進行處理、保存等。本文以莎車污水處理項目為例,介紹了城市污水處理工藝、上位監控計算機的綜合應用程序開發、城市污水處理自動控制系統plc控制站的設計和採用profibus系列中廣泛應用於現場設備的profibus - dp總線。
  7. After analyzing and comparing different partition rules, md32 pipeline architecture is finally defined, which meets the required instruction function, frequency and timing spec of md32. a complete set of creative design method for risc / dsp md32 micro - architecture is presented, such as parallel design, internal pipeline, central control, etc. thanks to the adoption of these design methodology, control path and data path are separated, circuit delay is reduced, and complex instruction operations are balanced among multiple pipeline stages

    它們將若干復雜操作均勻分配在幾個水節拍內完成,實現了任意窗口尋址等復雜操作,將整個處理器的通路與控制通路分離,減小了電路時延,從而滿足了risc dsp不同功能和系統時鐘頻率的要求,構成了統一的、緊密聯系的、協調的md32系統結構。
  8. ( 2 ) research the instruction launch strategy, controls correlation processing and data correlation processing of 32 - bit mips ’ s double - launching pipeline. obtained the design modes : static launch, optimized compile instruction, 1st pipeline jump and branch processing and double pipeline four channels front data path. ( 3 ) achievement designs by the platform xilinx ise 5. 2i, uses the verilog hardware description language to carry on the design description to the double - launching

    ( 2 )對基於32位mips架構雙發射水線的發射策略、控制相關處理和相關處理等水線結構的重要問題進行深入研究,並得出了靜態發射、優化編譯序、第一水線無延遲分支處理和雙水線四通道前向通路等一系列能夠與32位mips架構相匹配的雙發射
  9. The experimental results indicate that it is feasible to applied at - speed current testing to at89c51 microprocessor at instruction level. through testing of data paths, we can not only detect the faults arose by data path, but also find the faults brought in by control parts

    實驗結果表明,用全速電測試在級對at89c51微處理器進行測試是可行的,通過測試所有的通路,不僅可以檢測通路的故障,而且可以檢測由於控制錯誤而引起的傳送錯誤。
  10. Generally, the disassembly strategy can be divided into the liner - scanning strategy and recursion - scanning strategy based on control flow. through researching on the recursion - scanning strategy based on control flow and instruction sets of many processors, this essay proposes a kind of disassembly strategy based on the static program flow traversal graph, and makes use of six strategies to pick up the hidden program sections from the data sections, thereby raising the precision of the disassembly result

    反匯編策略大體可以分為線性掃描策略和基於控制的遞歸掃描策略,該文通過對基於控制的遞歸掃描策略以及多款處理器系統的研究,提出了一種基於程序靜態程遍歷圖的反匯編策略,使用6種策略將隱匿於段中的程序段提取出來,提高了反匯編結果的精確度。
  11. Watch simd devil at it ' s very best

    擴展可讓處理速度更快些。
  12. Sse streaming simd extensions

    單一擴充
  13. On the other hand, with a ppp modem scenario, your firewall is the router itself, with the route command directed to send all non - local traffic to the ppp port

    另一方面,利用ppp的機方案,防火墻就成為路由器,路由把所有非本地轉發到ppp埠。
  14. The dataflow display module is a graphic interpreter. it interprets the microinsmiction

    圖形解釋運行系統解釋並以的形式運行微
  15. What this basically means is that the instruction stream doesn ' t really change all that fast, but the data stream changes constantly

    一針見血的來講就是說的變化遠遠比不上的變化。
  16. For each register we create a queue and the index of queue item means a function of executing time. the item in the queue is either null or an instruction whose operand is kept in this register

    該演算法利用寄存器隊列分析間的相關,能夠分析出間的所有寄存器相關,其特點是:驅動;演算法簡單、實現效率高;并行成分的表示直觀。
  17. Simd single instruction multiple data

  18. The research work introduced in this paper mainly concerns the processor core design for media soc. media enhancement backward extension to mips - i compatible isa is presented in this paper. based on the analysis of inherent characteristics of media application algorithms, the basic mips - i compatible isa is extended to support sub - word parallel simd operation, special result handling, and dedicated media instructions

    在國家863計劃的支持下,我們開展了系統晶元中媒體增強的字信號處理器核的設計研究,本文作為部分成果,著重探討了處理器核集結構的媒體處理增強、處理器核微結構的設計和優化以及系統總線設計和媒體調度的問題。
  19. In this paper we propose a new simple approach for analyzing data dependence on dlx code using register queues

    與常用的基於圖的方法不同,我們提出了一種通過寄存器隊列檢測間寄存器相關的演算法。
  20. Due to the intrinsic property of no status bar of browser, b / s structure ' s network exam system leads to the great flow of the data, delays the control instruction of service port as well as appears exception of the function and data

    結構的網路考試系統由於瀏覽器無狀態的固有屬性,導致了考生考試期間量大,從而可能造成服務端控制的延遲,導致功能和異常。
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