文件寄存器 的英文怎麼說

中文拼音 [wénjiànjìcúnqì]
文件寄存器 英文
file register
  • 文 : Ⅰ名詞1 （字） character; script; writing 2 （文字） language 3 （文章） literary composition; wri...
  • 件 : Ⅰ量詞（用於個體事物） piece; article; item Ⅱ名詞1. （指可以一一計算的事物） 2. （文件） letter; correspondence; paper; document
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 文件 : 1 （公文、信件等） document; file; papers; instrument 2 [自動化] file; 文件保護 file protection; ...
  1. Two other effects are transient phenomenon called single event upset ( seu ) and single event latchup ( sel ). in this paper, some means to harden the devices against these phenomena are used. guard banding around nmos and pmos transistors greatly reduces the susceptibility of cmos circuits to lachup

    在本文設計中，採用雙環保護結構，大大的降低了cmos集成電路對單粒子閂鎖效應的敏感性；對nmos管採用環型柵結構代替傳統的雙邊器件結構，消除了輻射感生邊緣寄生晶體管漏電效應；採用附加晶體管的冗餘鎖存結構，減輕了單粒子翻轉效應的影響。
  2. The chip simulation network laboratory system this paper disguessed is a distribute network simulation system based on lan. the system ' s architecture is a c / s of three lays. the front platform are the chip simulation network system application program terminer ; the middle lay is a dcom server, it ' s duty is to deal with the communication and data transmission between the terminer and then database server, and to execute the logical operation. the application program just connect with the middle lay and get data from it, the connection and operation with database server will be managed by the dcom server. the duty of database server is to access and backup the final data

    具體是由位於網路各個終端的晶元模擬網路實驗系統應用程序為前臺；中間層為dcom應用程序服務器，負責處理前臺應用程序與后臺數據庫的通信和數據傳輸，並執行業務邏輯，前臺應用程序只需要與應用程序服務器建立連接，在中間層操作數據即可，與后臺數據庫的連接和操作由應用程序服務器來統一管理操作。后臺數據庫只負責數據的存取操作。本論文實施的晶元模擬網路實驗系統模擬了主要的邏輯電路器件， 8088cpu ，存儲器，寄存器，數據總線，地址總線和控制總線，及其它相關晶元。
  3. Not only fault model, but also test arithmetic demand to be farther improved. the thesis, focusing on the 20 - port register file, makes a fault analysis, particularly in complex bridge fault and crosstalk coupling fault aroused by word - line and bit - line of 20 - port

    本文針對所設計的寄存器文件進行了故障分析，特別對20埠字線、位線引起的復雜橋接故障和串擾導致的耦合故障進行了詳盡論述。
  4. In this paper, we discuss a kind of filter generator whose filter functions have less input bits than the degree of the linear feedback shift register ( lfsr ). by analyzing the structure of the filter generator and its equivalent system, we give out a conditional search algorithm ( csa ) to attack this kind of filter generators

    針對濾波函數f （ x ）的輸入比特數m少於線性反饋移位寄存器級數n的濾波生成器，本文通過分析其等價的組合生成器的結構，以及不同節拍上驅動序列的各個符號之間的制約關系，給出了廣義解序列的概念，並提出了類似遍歷二叉樹的條件搜索演算法csa ，用於攻擊該類特殊的濾波序列。
  5. Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. from the layout simulation result, under the 0. 18um process, the upper limit working frequency for the register file is 900mhz

    本文面向一款具有完全自主知識產權的64位高性能通用處理器，對其中具有代表性的128字65位12讀埠和8寫埠的通用寄存器文件進行研究，實現了它的高速讀寫全定製設計，版圖模擬結果表明，在0 . 18um工藝下，設計可以工作的時鐘頻率上限為900mhz 。
  6. This includes initializing hardware registers, identifying the root device and the amount of dram and flash available in the system, specifying the number of pages available in the system, the filesystem size, and so on

    這包括初始化硬體寄存器、標識根設備和系統中可用的dram和閃存的數量、指定系統中可用頁面的數目、文件系統大小等等。
  7. These results are then committed to a separate architectural register file during in - order retirement

    這些結果然後在有序退回時，存放在一個獨立的結構寄存器文件中。
  8. In the data path, many modules were designed and implemented, such as alu. data bus unit, w ( work register ) and registers file. the designs of peripheral functional modules were finished, including usart, spi and io

    在詳細分析riscmcu的體系結構特點的前提下，進行了系統劃分，並詳細設計了該riscmcu的數據通路，包括設計該數據通路上的alu單元、內部數據總線、工作寄存器w以及寄存器文件等功能模塊。
  9. In the second part, this paper does deeply research on how to use the memory system effectively. firstly, this paper proposes a modified register allocation via graph coloring to alleviate port conflicts

    然後，面對分體寄存器文件可能產生埠沖突的新問題，提出了改進的基於圖著色的寄存器分配法。
  10. Optimizing with profile data results in better register allocation. basic block optimization

    寄存器分配用配置文件數據進行優化，可以實現更好的寄存器分配。
  11. This supports a 40 - entry physical register file that holds temporary write - back results that can complete out of order

    此支持40種物理寄存器文件，此文件含有能混序完成的臨時回寫結果。
  12. In the first part, this paper discusses the key problems in designing architecture of each component, which include why we choose partitioned regiater files, use 2 - way connected data cache with write - back strategy and add scratch - pad sram to original momory system, and how to identify their parameters. following that, a memory configuration based on the discussion above is presented

    本文首先介紹了dpc各個存儲器的設計和實現，詳細討論了寄存器文件分體結構的選擇並提出了寄存器文件參數配置的四條規律，介紹了數據cache容量及策略的權衡與選擇，闡述了scratch - padsram與cache並存的優勢。
  13. With software and hardware co - design method, this paper proposes an algorithm to calculate register lifetime in programs, and the control of writing results back into rf is implemented through an enable control signal provided by instruction encoding at compile time

    基於軟硬體協同設計的思想，在研究局部變量生存期演算法的基礎上，本文提出了通過編譯器指令編碼實現對硬體結構的使能控制，即控制流水輸出結果是否寫回寄存器文件，以減少對寄存器文件的寫次數，從而降低寄存器文件埠的讀寫壓力。
  14. From the born of microprocessor to now, register file as its key part, requires higher read and write access speed. but, along with the development of the register file directing to large - scale and multi - port, realizing a high speed design becomes a difficult problem nowadays

    微處理器誕生至今，寄存器文件作為其內核關鍵部件，往往需要很快的讀寫訪問速度;但是隨著寄存器文件向著大規模、多埠方向發展，實現高速讀寫成為了當前研究的一個難題。
  15. Abstract : the main points about development of application programs based on visa for vxibus are presented, including addressing an instrument, accessing a message - based device and a register - based device, handling events and errors. some practical programs are presented

    文摘:介紹了利用visa庫進行vxi總線編程的幾個要點，包括儀器的尋址、消息級器件的訪問、寄存器級器件的訪問、異步事件處理和出錯處理等，並給出了示常式序。
  16. The configure file is downloaded into the fpga chip according to the fpga design fl ow. also a test system is set up, and the work status of the system is controlled by single chip to download the data of initial registers and control registesr. and the logical analyzer is used to sampling the output signals

    使用xillinx的fpgaxc2550pq208 ，經過fpga的實現流程，把配置文件配置到xczs5opqzos ，搭建了一個驗證系統，通過單片機來對各控制寄存器寫入控制字來控制系統的工作狀態，用邏輯分析儀採集輸出的信號。
  17. In system emulator, atmega monolithic processor compatible

    內部外部ram內部寄存器文件
  18. Then, the thesis, based on march c - algorithm, shadow read and shadow write technologies, put forwards bist arithmetic for the 20 - port register file

    之後本文在marchc -演算法的基礎上，結合shadowread和shadowwrite技術，首次提出了針對20埠寄存器文件的bist演算法。
  19. Otherwise, as a memory component, large - scale register file holds a large number of data, so it requires stronger stability and validity. for memory components, using bist method to make a fault checking is a relatively good choice. but the bist of the multi - port register file is still in early phase of development

    另外作為存儲部件，規模大的寄存器文件現場保存量大，需要有很強的穩定性和正確性，而內建自測試是存儲部件進行故障檢測的較佳選擇;但是多埠寄存器文件的測試卻處在初始發展階段，故障模型和測試演算法都有待于進一步完善。
  20. 2, design and realization the data - path of armp processor. including arithmetic logical unit ( alu ), register files. shifter, multiplier and so on

    2 、對armp中數據通路的設計與實現：包括alu的設計、寄存器文件（ registerfile ）的設計、移位器（ shifter ）的設計、乘法器的設計等等。
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