時序模擬器 的英文怎麼說

中文拼音 [shíxùmónǐqì]
時序模擬器 英文
timing simulator
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 擬 : 動詞1. （設計; 起草） draw up; draft 2. （打算; 想要） intend; plan 3. （模仿） imitate
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 時序 : [地質學] sequence; sequential; time sequence; timing sequence; sequence in time
  • 模擬器 : emulator
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  1. The main research advances can be summarized as follows : ( 1 ) study the signal processing ' s performances and methods of homing torpedo system comprehensively, in order to setting up a corresponding mathematical models ; ( 2 ) analyze the ocean channel ' s effects on the work of homing system, then found some models such as target echo signal, noise ( including background noise, target radiating noise, etc ), ocean reverberation. according to them, simulate the array signal ; ( 3 ) the system structure, every function blocks composing are studied and founded thoroughly. then, discuss methods of signal processing in time domain and airspace domain ; ( 4 ) program the simulation software of torpedo ' s homing system according to the simulation models and flow charts, which connected with torpedo ' s control part

    本文所作的主要工作及研究成果主要有以下幾個方面： （ 1 ）對自導工作過程中的信號與信息處理的基本理論與方法進行了較為全面的研究，為建立一個較為完備的自導模擬系統提供了理論基礎； （ 2 ）討論了自導系統工作過程中海洋通道對目標回波信號與目標輻射噪聲信號等的影響，建立回波信號的數學模型、環境場中的噪聲信號模型（包括海洋環境噪聲、目標輻射噪聲與魚雷背景噪聲等）與海洋混響模型，模擬產生了聲自導系統基陣接收到的回波信號與噪聲信號； （ 3 ）深入研究並建立了自導模擬系統的總體框架，給出各個具體功能模塊組成，討論了聲自導系統對信號的時域與空域處理，並結合模擬程序中陣列信號處理模塊，給出固定多通道波束形成的模擬實現過程； （ 4 ）根據系統的模擬模型與已建立的模擬流程圖編制了通用魚雷模擬器自導系統模擬軟體，通過網路與控制系統相連，組成完整的魚雷模擬器。
  2. The design of this chip sticks to the general methodology of hdl design. lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route. the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done. the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl

    在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim模擬器完成了功能模擬，使用synopsys的fpgacompiler進行了基於alterafpga庫的網表綜合，最後將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim模擬器中進行了時序模擬，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。
  3. In this dissertation, correlative research of longer - term voltage stability have been carried out, including some slow dynamic elements, such as on - load tap changer ( oltc ), maximum excitation limiters ( mel ), etc. the effects of these slow dynamic elements on the course of voltage instability or collapse are revealed from the point of view of time - domain simulation

    本文基於pss e程序中的擴展動態模擬模塊，對考慮有載調壓變壓器（ oltc ） 、最大勵磁限制器等慢動態元件的中長期電壓穩定進行了相關的研究，從時域模擬的角度揭示這些慢動態元件在電壓崩潰過程中所起的作用。
  4. Plc system is composed of manage computer, master device and i / o modules. programme software runs in windows - based manage computer system and it has many functions, such as hardware configuration, editing with ladder diagram, simulated running of control programs, communications with master device, and so on. this software is a necessary tool of editing control programs, debugging control programs and real monitoring for plc system designer

    Plc系統由上位機、主控制器和i / o模塊等組成，編程軟體運行於上位機系統windows2000平臺，具有系統硬體配置、梯形圖程序編輯、控製程序模擬運行以及與主控制器通信等功能，是plc系統設計人員編制、編輯、調試plc控製程序以及實時監測現場運行狀況的必備工具。
  5. When an emulator supporting user - mode emulation encounters a system call instruction, on the other hand, it does not transfer control to the emulated exception handler ; instead it interprets the system call itself

    另一方面，當一個支持用戶模式模擬的模擬器碰到一個系統調用指令時，它並不是把控制轉交給模擬的異常處理程序，相反，它會自己解釋該系統調用。
  6. It had also used vhdl language to carry through the timing simulation about hvct and digital clock. the simulation had the same result to the theory. it had established stability foundation to the future chip simulation

    並以實際應用為例，用其對高壓電流互感器和數字鐘進行了時序模擬，模擬結果與理論一致，為進一步的晶元模擬奠定了堅實的基礎。
  7. Between mathematics inferential result and programmer simulation result, we can see that they are consistent. thus proof our network - level routing protocol is feasible and has the merit of consuming energy equably while saving energy when the wireless sensor network is working

    在理論推導結論和程序模擬結果中，我們可以看出，二者結論相符，從而驗證本文所改進的無線傳感器網路網路層路由協議的可行性，驗證了在無線傳感器網路工作過程中，節點能夠在節省能量的同時相對均勻地消耗能量的優點。
  8. It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function

    本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。
  9. At last, i have also resoved the problem of connector with main program of driving simulator, and done convection of the data of traffic flow

    最後解決了與駕駛模擬器主程序的介面，完成了交通流數據的實時傳送。
  10. Because the program running time on the simulator is not the real system ' s running time, a method to compute the time has been designed, thus the real running time can be calculated after the program runs over

    由於在模擬器上程序的運行時間不是真實系統的執行時間，所以我們設計實現了計算時間的方法，可以在程序結束時給出程序的真實執行時間。
  11. Then the designs of modules mentioned in the scheme are discussed in detail. the main contents of the dissertation include : 1. to satisfy the need of a16 / d16 single - cycle and block data transfer capability, the method of the state machine and diagram are adopted. the arbiter, requester, interrupter, interrupter handler modules are also implemented by use of the state machine. these modules are verified theoretically by using timing simulation

    本文具體工作如下: 1 .用狀態機和電路圖的方式實現了vme總線a16 / d16單周期數據讀寫和塊傳輸功能;並用狀態機設計了vme總線請求器，總線仲裁器，中斷器和中斷處理器等，並進行了時序模擬。
  12. Its premise is pci bus specification and its sticking point is to analysis the function and architecture of pci bus controller. this dissertation finishes the design of pci bus controller, and it has also completed the function simulation of this module as well as timing simulation and a pcb card for test which prove it rightness at last

    通過本論文的研究，完成了pci總線控制器的設計，並且通過編寫測試激勵程序完成了總線控制器功能模擬，以及布局布線后的時序模擬，並設計了pcb實驗板進行了測試，證明所實現的pci目標控制器完成了要求的功能。
  13. The automatic test vector generation method based on fault simulation is described, and the whole procedure of atpg of sequential circuits is analyzed, fault simulator - hope as an example

    本文闡述了基於模擬的自動測試生成方法，以故障模擬器? hope為例分析了整個時序電路自動測試生成過程。
  14. Base on the existing synchronous sequential circuits fault simulator - hope, the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly

    本文在同步時序電路故障模擬器? hope的基礎上，率先對基於螞蟻演算法的時序電路測試矢量生成方法作了系統的開拓性研究。
  15. In the illustrative example, this approximate feedback design is shown to be robust and effective in controlling a nonisothermal tubular reactor at possibly realistic situations

    當考量接近實際程序的情形時，由模擬結果印證此近似的回饋設計是具有韌性且能有效控制一非等溫管狀反應器程序。
  16. This is one kind project of hardware multiplexer based on the high - performance system on a programmable chip ( sopc ). in the project author integrate with the software and the hardware on a field programmable gate array ( fpga ), not only simplifying the overall system design, moreover realizing stably, high speed, low cost multiplexer ’ s design. the dissertation carry on three verification step that include function verification 、 time verification and prototype verification to guarantee each ip can work normally to satisfy the system performance requirement. then author introduce the realization of the multiplexer in detail, as well as the test and the debugging questions met in practice and solution of the questions

    本方案是一種基於可編程片上系統（ sopc ）的硬體復用器設計方案，其特點是將系統的軟體和硬體集成在一款現場可編程門陣列（ fpga ）上，使用該方案不但簡化了整個系統，而且實現了穩定、高速、低成本的復用器設計。對系統中各個功能模塊的整合和驗證採用功能模擬、時序模擬、原型驗證三個步驟進行，保證系統中各個功能模塊可以正常工作，並滿足系統的性能要求。然後詳細介紹了復用器的實現，以及測試和調試中遇到的問題及解決方法。
  17. In the fec part, rs ( reed - solomon ) code and interleave are chosen as the basic elements of the error correction system at first ; then the coding parameter and data structure are determined based on the results of matlab simulation ; at last, hdl modules are implemented in fpga using verilog hdl, test results and simulation diagrams are presented as well. in the designing process, the proper division of the modules and the cooperation between modules need a lot of consideration, and the top - down method is adopted to solve these questions

    在前向糾錯的設計部分，文章首先根據系統的誤比特率要求選擇了rs （ reed - solomon ）碼和交織器作為前向糾錯部分的基本構架，再根據matlab的模擬結果得到了具體的編解碼參數和碼字結構，最後在fpga中用硬體描述語言veriloghdl實現了各個編解碼模塊，並給出了測試數據、實現結果及時序模擬波形圖。
  18. This dissertation finishes the design of pci bus target controller, with vhdl description of register transfers level. and it has also completed the function simulation as well as timing simulation after placing & routing. a fpga on pcb board is designed to test the target controller and the result of test meets basal function demand

    本論文完成了pci總線目標設備控制器的設計，採用vhdl對其進行了rtl級的描述，並且通過編寫測試激勵程序完成了功能模擬，以及布局布線后的時序模擬，通過fpga在pcb實驗板上進行硬體模擬，證明所實現的pci目標設備控制器符合基本功能要求。
  19. After a series of functional and time delay simulations, the design proved to be feasible and effective. the application indicates that the scheme is reasonable and the pxi - bus counter module meets the requirements of the design

    本文對pxi計數器的各項功能進行了功能模擬和時序模擬，並對其進行了調試和測試，測試結果表明:模塊設計方案合理、各項功能與指標均滿足設計要求。
  20. Based on researching viterbi decoding algorithm, i design viterbi decoder on fpga using quartusii design platform of altera to design vhdl program, synthesis, simulate function logic and simulate time logic

    本設計在viterbi演算法研究基礎上對viterbi譯碼器進行fpga設計，採用altera公司的quartusii開發工具為系統開發平臺，在此平臺上進行vhdl設計、綜合、功能模擬和時序模擬。
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