時序邏輯語言 的英文怎麼說

中文拼音 [shíxùluóyǔyán]
時序邏輯語言 英文
temporal logic language
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 語 : 語動詞[書面語] （告訴） tell; inform
  • 言 : Ⅰ名詞1. （話） speech; word 2. （漢語的一個字） character; word 3. （姓氏） a surname Ⅱ動詞（說） say; talk; speak
  • 時序 : [地質學] sequence; sequential; time sequence; timing sequence; sequence in time
  • 邏輯 : logic
  • 語言 : language
  1. The semantics and generalized tautology of fuzzy temporal logic

    模糊時序邏輯的語義及其廣義重言式
  2. The 10th australian joint conference on artificial intelligence, perth, australia, 1997, pp. 38 - 43. 7 he m, leung h f, jennings n r. a fuzzy logic based bidding strategy in continuous double auctions. ieee transactions on knowledge and data engineering, 2003, 15 : 1345 - 1363

    為了祛除關于信息的不現實的假定，對不確定信息進行描述和推理，在本文中，以概率論為描述不確定信息的理論基礎，提出了一種新的面向agent的概率邏輯程序語言，它把概率程序和實時程序結合起來。
  3. Up to now, there has been ten years for the research of dynamic fuzzy logic ( dfl ) and a series of achievements have been made. in order to further expand the applications of dfl, this thesis followed dijkstra ’ s guarded commands and put forward an operational semantics model of dfl programming language which can solve dynamic fuzzy problems

    動態模糊邏輯（ dfl ）的研究已有十年的時間了，目前已取得了一系列研究成果，為了進一步拓展這些研究成果的應用，本文借鑒dijkstra的監督命令程序結構，通過結構化操作語義描述方法從軟體理論方面進行研究，提出了動態模糊邏輯程序設計語言（ dflprogramminglanguage ）的操作語義模型，以期形成解決動態模糊性問題的程序設計方法。
  4. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  5. We use temporal logic language xyz / e as our component description language for components may have different abstract hierarchy and different granularity. xyz / e is able to describe the dynamic semantics and static operations of component, and to formally describe system in different hierarchy

    由於構件可能具有不同的抽象層次和粒度，我們採用了時序邏輯語言xyz e作為構件描述語言，這種語言能夠描述構件的靜態語義和動態執行，並且能在不同抽象層次上對系統進行形式化描述。
  6. The article all so try to look out the problems in the fables system of the chinese teaching material, and try to investigate and research the problem, all this based on thinking of the characteristic of chinese teaching, the characteristic of the times, the logic array of the knowledge and the developing regulation of the students, and so on

    本文通過對語文教材選用寓言的必要性、可行性進行分析，認識寓言對教材建設、教師教學、學生學習的重要意義，並綜合考慮時代的特點、知識邏輯序列、語文學科的特性、學生身心發展規律等諸多因素，嘗試對現行語文教材中寓言體系所存問題進行調適研究。
  7. I regard qsim as a kind of constraint satisfaction problem ( csp ), and improve the qualitative simulation algorithm by constraint logic programming ( clp ). fuzzy qualitative simulation develops conventional qsim on several facets, such as representation of qualitative value, state transition rule and filtering algorithms. it bridges the gap between pure qualitative and quantitative, and improve the efficien

    前者是將定性模擬演算法看作一類約束滿足問題，用約束邏輯程序加以改進，不僅為解決定性模擬問題提供了邏輯框架，而且也是一種規范化的程序描述語言；模糊定性模擬演算法則是對純定性模擬演算法在知識描述、狀態轉移規則、過濾演算法等方面的改進，是一類半定量描述方法，有利於在定性模擬領域綜合定量信息，同時提高演算法的效率。
  8. So, in this paper, it does the research of the bidirectional conversion between uml and xyz / adl. in this way it combines the oo visual modeling language and formal method based on temporal logic together to describe software architecture, and so to find how to apply the formal method to real software development to promote the research not only on main technologies in software but also on formal method

    基於此，本文開展了對基於時序邏輯的軟體體系結構描述語言xyz / adl和uml之間的雙向轉換問題的研究，通過研究二者之間的轉換，實現將基於時序邏輯的形式化方法與面向對象的可視化建模語言相結合描述軟體體系結構，來探討如何將形式化方法應用於實際的軟體開發過程中，這樣不但能促進對當前軟體主流技術的研究，而且能促進對形式化開發方法的研究。
  9. While programs in the java language are theoretically immune from " memory leaks, " there are situations in which objects are not garbage collected even though they are no longer part of the program s logical state

    雖然用java語言編寫的程序在理論上是不會出現「內存泄漏」的，但是有時對象在不再作為程序的邏輯狀態的一部分之後仍然不被垃圾收集。
  10. This paper composes a new way to describe software architecture through combining the visual modeling language which is object oriented and the formal method which based on temporal logic. it contributes to the research of software architecture description and the research of formal semantics of uml as well as the application of formal method in the software development

    本文通過將面向對象的可視化建模語言與基於時序邏輯的形式化方法結合起來描述軟體體系結構，對軟體體系結構描述研究、 uml形式語義研究和形式化方法在軟體開發中的應用等方面都有一定的推動作用。
  11. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
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