時序邏輯 的英文怎麼說

中文拼音 [shíxùluó]
時序邏輯 英文
sequential logic時序邏輯電路 sequential logical circuit; 時序邏輯方程 sequential logic equation
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 時序 : [地質學] sequence; sequential; time sequence; timing sequence; sequence in time
  • 邏輯 : logic
  1. The semantics and generalized tautology of fuzzy temporal logic

    模糊時序邏輯的語義及其廣義重言式
  2. In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework

    另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。
  3. In addition, a novel heuristic approach which we called “ improved simulated annealing algorithm ” is proposed for bounding maximum and minimum leakage power. 2. a design method for low power clock network is proposed

    通過對高性能通用處理器中時序邏輯特點的詳細分析，提出採用帶門控使能的多比特觸發器設計方法來降低時鐘功耗。
  4. 4. interval temporal logic ( itl ) is a temporal logic which includes a basic construct for the sequential composition of two formulas as well as an analog of kleene star

    間斷式時序邏輯（ itl ）是時序邏輯的一種，它包含一個由兩個公式的連續成分所構成的基本結構和一個kleene星的類似體。
  5. In fact, we use the digital way directly to synthesize sine wave

    摘要數字電路技術課程的知識難點是時序邏輯電路的設計。
  6. In this paper, interval temporal logic is applied to represent the hybrid systems

    本文運用間斷式時序邏輯表達和建立水工業系統模型。
  7. The systems are usually described by the timed automata and the properties are specified by the temporal logic

    這類系統通常用時間自動機來表示，而它們的性質則用時序邏輯公式表示。
  8. The thesis offers apd signal amplify circuit chart and controlling time - series logic circuit principle chart bearing practical applied value

    給出了apd信號放大電路和控制時序邏輯電路原理圖。
  9. For seminal work introducing temporal logic into computing science and for outstanding contributions to program and systems verification

    他將時序邏輯引入計算機科學，為程序和系統的檢測驗證方面提供一種有力的工具。
  10. It is easier for us to realize the hardwave circuit, and the content of sine wave at least by 45db is the projecting advantages

    本文主要論述一種實用的時序邏輯電路的設計與實現設計一個十字路口交通燈自動循環亮滅的控制器。
  11. Complex programmable logic device ( cpld ), usually used to develop asic, is widely used in digital system to accomplish complex combinational and sequential logic

    復雜的可編程邏輯器件（ cpld ）廣泛地用於數字系統中，常用作設計自己的專用集成電路，可實現復雜的組合邏輯和時序邏輯。
  12. The tool mr barth is employing to effect this transition is linear temporal logic, a system of mathematical logic that can express detailed constraints on the past and the future

    巴斯先生用來實現這一轉化過程的工具是線性時序邏輯，一種可以表達過去和未來的詳細約束的數理邏輯系統。
  13. The thesis analyses the problems on the noise of apd photoelectric receiving system. author designs apd laser signal receiving system circuits, front amplify circuit, controlling time - series logic circuits, dc / dc transform circuits. and takes apd bias voltage fuzzy control

    分析了apd光電接收系統的噪聲問題，並對apd激光信號接收系統電路、前置放大電路、控制時序邏輯電路、 dc / dc變換電路進行了設計，採取了apd偏壓模糊控制。
  14. Conditional sensitization of paths is presented from the sensitization theorem of sequential circuits and a novel exact clocking method based on single - period sensitization is proposed. compared with tranditional methods, it is not too optimistic or pessimistic, fit for the exact timing of high - speed circuit design

    在時序邏輯電路精確定時方面，從時序電路的敏化定理出發，使用本文給出的條件可敏化概念，通過對通路敏化性質的判斷建立了一種新的單周期敏化的時序電路最小時鐘周期精確確定方法。
  15. Digital circuit includes two kinds - the assembly logic circuit and the sequential logical circuit, the characteristic of the assembly logic circuit is that the output signal is only the function which enters the signal and has nothing to do with the entering state at any other moment, it has no function of memory

    摘要數字電路分為組合邏輯電路和時序邏輯電路兩類，組合邏輯電路的特點是輸出信號只是該時的輸入信號的函數，與別時刻的輸入狀態無關，它是無記憶功能的。
  16. We use temporal logic language xyz / e as our component description language for components may have different abstract hierarchy and different granularity. xyz / e is able to describe the dynamic semantics and static operations of component, and to formally describe system in different hierarchy

    由於構件可能具有不同的抽象層次和粒度，我們採用了時序邏輯語言xyz e作為構件描述語言，這種語言能夠描述構件的靜態語義和動態執行，並且能在不同抽象層次上對系統進行形式化描述。
  17. The broadband signal is generated by high speed d / a, and the logical control of the system such as the interface timing control of ide or sdram is implemented by fpgas

    採用高速d / a實現輸出信號的高寬帶，採用多片fpga完成整個系統的時序邏輯控制，比如ide介面時序的實現， sdram的操作等。
  18. In data sampling circuit, high - speed, complex programmable logic device cpld technique is used. high - speed double - port ram, control sampling time sequence logic, cpu interfaces and bus circuit are implemented in cpld. sampling speed is up to 80mhz, sampling depth is ik - byte, and cpld can fulfill the requirement of the software arithmetic to sampling

    在數據採集電路中採用了高速復雜可編程邏輯器件cpld技術，晶元內設計有高速雙埠ram 、控制采樣時序邏輯及cpu介面、總線等電路，采樣速率高達80mhz ，采樣深度1k位元組，很好地解決了超聲波微位移傳感器軟體演算法對采樣的要求，並可實現在線升級，大大提高了系統的整體性能。
  19. So, in this paper, it does the research of the bidirectional conversion between uml and xyz / adl. in this way it combines the oo visual modeling language and formal method based on temporal logic together to describe software architecture, and so to find how to apply the formal method to real software development to promote the research not only on main technologies in software but also on formal method

    基於此，本文開展了對基於時序邏輯的軟體體系結構描述語言xyz / adl和uml之間的雙向轉換問題的研究，通過研究二者之間的轉換，實現將基於時序邏輯的形式化方法與面向對象的可視化建模語言相結合描述軟體體系結構，來探討如何將形式化方法應用於實際的軟體開發過程中，這樣不但能促進對當前軟體主流技術的研究，而且能促進對形式化開發方法的研究。
  20. The method of model checking is a formal verification technique using the method of state - space search to verify if the behaviors of a given system ( the model ) satisfy a certain property that represented by temporal logic formulas, while the system presented as a kripke structure

    它通常採用狀態空間搜索的方法來檢測一個給定的計算模型是否滿足某個用時序邏輯公式表示的特定屬性。它是一個自動檢驗有限狀態並發系統的技術。
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