時鐘信號線 的英文怎麼說

中文拼音 [shízhōngxìnháoxiàn]
時鐘信號線 英文
clock cable
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 號 : 號Ⅰ名1 （名稱） name 2 （別號; 字） assumed name; alternative name3 （商店） business house 4 （...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  1. The speed with which your microcomputer executes programs will vary linearly with the speed of your clock signal.

    你的微型計算機執行程序的速度將與你的時鐘信號的速度成線性關系。
  2. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  3. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬信號調理模塊對輸入的信號進行調理，以達到系統和模數轉換器（ adc ）采樣的要求; dsp作為系統的核心部件，外擴了adc 、以太網控制器、 rs - 485總線收發器、 can總線收發器和時鐘晶元， dsp對實時數據進行處理，當報警發生時將實時數據通過以太網上傳給上位機。
  4. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  5. Gps is a planet wireless conductance system which is global and all - weather, gps can offer high precision time orientation information to infinite user, clock precision reachs 10 ? 6 magnitude 。 not only changes traditional time method of quartz crystal clock, but also replaces wireless shortwave and even more lowfrequency signal and tv signal whose overlay range is limited and low precision, offers advantage to geology field task, achieve automatization and high precision of seismic flow observation

    利用gps授時信號全方位、全天候、連續性、實時性和高精度的特點，以gps信號為基準來校準本地時鐘（晶體振蕩時鐘或原子鐘） ，將gps接收機輸出信號的長期穩定度和恆溫晶振的短期穩定度相結合，應用大規模可編程邏輯器件，設計和實現了由pc104控制的實時在線授時系統。
  6. The precise clock source is crystal oscillator made of 74hc04 ; the mute circuit can conceal the error and solve the problem of noise ; the antenna switching circuit in the receiver is to select one antenna from two which receives signal better. it can improve the quality of the receiving audio signal, restrain the noise effectively and promote the system performance

    高精度的時鐘源是由74hc04構成的晶體振蕩器;靜音電路將出錯的音頻信號進行差錯掩蓋，很好地解決了噪聲問題;接收機採用兩副天線切換工作，提高了音頻信號接收質量，有效地抑制干擾，提升了系統的性能。
  7. Supports external wait signal to expend the bus cycle

    支持外部等待時鐘信號延長總線周期。
  8. Traces on opposite sides of the board should run at right angles to each other

    快速切換的信號，例如時鐘信號，應該用地線屏蔽，以避免將噪聲輻射到其他部分。
  9. This logic is designed containing input signal delay, event type classification, event pre - scaling and timing logic and works in pipeline mode under control of 20mhz clock which ensures no dead time contribution

    主觸發邏輯在20m時鐘下以流水線的方式工作，保證沒有死時間的產生。第二個例子是任意數字信號發生器的設計。
  10. Horology. time transmission from masterclock to secondary clocks by coded signals on double - wound. requirements

    鐘表業.在雙繞線上用編碼信號從母鐘到子鐘的時間傳送.要求
  11. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  12. Within this scope, users can get almost any frequency clock by configuring the register, as the tune - process is nearly continual ( in fact there are many discrete frequency points ). the main circuit of the clock generator is a cppll ( charge pump pll ) designed in a method

    該時鐘發生器可以向系統提供頻率范圍是93 . 75k - 180mhz的時鐘信號，用戶可以通過配置寄存器的方法使時鐘發生器輸出自己需要的頻率，而且這一調頻過程幾乎是連續的（實際上是眾多離散點構成的線性近似） 。
  13. System control module accomplishes many functions, such as systemic initialization, controling work of the system, man - machine interface and selecting channel. it communicates with other modules by i2c bus. timing signals are inputed into microprocessor through p1 port and control signals are provided through p2 port

    系統控制模塊和其他模塊間的通訊基於i ~ 2c總線，並利用了p1口進行各時鐘信號的檢測和利用p2口的各線作為控制線宋控制相應模塊的工作。
  14. Based on the coherent reception theory of radio signals and the theory of digital signal processing, the effects of carrier frequency offset, sampling clock offset, and symbol timing offset on ofdm signals are exploited. a series of amendments and new algorithms is derived from the in being algorithms of guard interval based symbol timing and frequency offset estimation, frequency - domain frequency offset, sampling offset, and symbol timing offset estimation

    以無線信號的相干接收和數字信號處理理論為基礎，就載波頻偏、采樣鐘偏差和符號定時偏差對ofdm信號的影響進行了分析，對基於保護間隔的符號定時與載波頻偏估計演算法和多種現有頻偏、采樣鐘與符號定時偏差的頻域估計演算法進行了研究，提出了一系列改進措施與新演算法。
  15. In this thesis, the principle of polarized light wave transmit in optical fiber is researched, i. e. principle of ternary optical fiber communication is researched. based on the researches, the construction of ternary codes optical end machine and 3b2t optical end machine used in two - state fiber net are designed. the construction and component of circuits in 3b2t optical ( called sign converter circuit - scc ) are designed particularly, including : the clock synchronization module, the data synchronizing, code converting module, frame managing module and error exam and managing module

    本文研究了線偏光波動理論以及在光纖中的傳輸原理，研究了三值光通信系統原理和器件原理；在此基礎上，設計了三值光端機和在現有兩值光纖網中實現三值光通信的3b2t三值光端機的組成結構，詳細設計了3b2t三值光端機的電路組成部分（稱為電信號變換電路scc ） ，包括：時鐘同步模塊、數據同步模塊、碼元變換模塊、幀處理模塊及差錯檢測和處理模塊；而且在三值光纖通信基礎上，提出了四值光通信的原理和偏分復用的實用化方法。
  16. In this paper, the method of in - bore abnormal phenomenon remote detecting is presented. considering of the multi - channel transient signals automatic acquisition, a project of pcm signal hardwire transmission data automatic acquire system is put forward. in this system, a pcm demodulate board is designed, it can decode the pcm code string which contain the information of the multi - channel transient signals, it also can catch the useful data automatically, and transmit these data to upper pc by rs485

    在該系統中，為了能夠解調出包含多路動態信號數據的高碼速率pcm信號，設計並製作了一種適用的pcm解調板，能夠從pcm碼流中恢復出位時鐘信號，從而與發送端保持位同步和幀同步，從而對pcm碼流可靠地解調、緩存，並能根據計算機設定的觸發條件自動地捕獲多路信號的有效段，然後利用rs485總線將這些數據可靠地遠傳至計算機以供顯示、分析和保存。
  17. The logical architecture, protocol, the encoder algorithm, the decoder algorithm and the electronics specification of the tmds which is the core of the dvi and means transition minimized differential signal are described in particular in this paper. and the synchronization and data recovering which mean the central problem in the high speed serial data communications are also analyzed

    本文以dvi介面通訊協議為主線，詳細介紹和分析了作為介面核心內容的tmds ? ?最小變化差分信號的邏輯架構、通訊協議的編碼演算法、解碼演算法、 tmds信號的電氣規范等問題，並著重分析了作為高速串列通訊的關鍵問題的鏈路時鐘同步與數據恢復問題。
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