時鐘輸入 的英文怎麼說

中文拼音 [shízhōngshūrù]
時鐘輸入 英文
clock i ut
  • 時 : shí］Ⅰ名1 （比較長的一段時間）time; times; days:當時at that time; in those days; 古時 ancient tim...
  • 鐘 : Ⅰ名詞1 （用銅或鐵製成的響器） bell 2 （計時器） clock 3 （指鐘點、時間） time 4 （沒有把兒的杯子...
  • 輸 : Ⅰ動詞1 （運輸; 運送） transport; convey 2 [書面語] （捐獻） contribute money; donate 3 （失敗） l...
  • 入 : Ⅰ動詞1 （進來或進去） enter 2 （參加） join; be admitted into; become a member of 3 （合乎） conf...
  • 時鐘 : [電學] [半] clock時鐘計數器 [自動化] clock counter
  • 輸入 : 1 （從外部送到內部） import 2 [電學] input; entry; entering; in fan; fan in; 輸入變壓器 input tra...
  1. The counter has been preset to 0000 and as the input "runs, " the counter advances by 1 bit per input pulse.

    計數器預置0000，並在時鐘輸入下計算每輸入一個脈沖計數器便累加10。
  2. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  3. The analog signals are regulated to satisfy the system and analog - to - digital converter ( adc ) ; dsp is the core part and is connected with adcs, a controller of ethernet, a rs - 485 bus transceiver, a can bus transceiver and a clock. the real - time data is disposed by dsp and is transferred to the upper computer when the alarm is happened

    模擬信號調理模塊對輸入的信號進行調理，以達到系統和模數轉換器（ adc ）采樣的要求; dsp作為系統的核心部件，外擴了adc 、以太網控制器、 rs - 485總線收發器、 can總線收發器和時鐘晶元， dsp對實時數據進行處理，當報警發生時將實時數據通過以太網上傳給上位機。
  4. Secondly, compared with some other kinds of comparator structure and based on the preamplifier - latch fast - compare theory, a novel topology of cmos preamplifier latch comparator circuit is presented. considering trade - off between kickback noise and power dissipation, reference resistance value is optimized. according to the encode demands of different stage resolution, clock - control encode circuit is designed

    其後，在具體的子adc設計中，對比各比較器類型的優缺點，並基於預放大鎖存快速比較理論，提出一種新型高速低功耗預放大鎖存比較器電路拓撲;根據adc系統所允許的參考電壓最大波動限制，在回饋噪聲對輸入參考電平的影響和功耗之間折衷，確定優化的參考電阻串阻值;根據不同級精度的編碼要求，設計出時鐘控制編碼電路。
  5. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  6. Chapter 3 treats the algorithm implementation of demodulator in the receiving asic of dvb - s. in detail, demodulation includes carrier recovery and symbol synchronization. together with the transmission characterization of band - limited input signals the chapter proposes a scheme for implementing carrier recovery loop

    解調具體分為載波恢復、時鐘同步兩大部分，本章著重論述了載波恢復的原理並結合dvb - s輸入信號傳輸特性，提出了相應的實現方案，對部分電路進行了性能分析。
  7. The level adjustment circuit 100 lowers the clock signal input to the first clock terminal ck1 by a predetermined value from h level and provides the signal to the gate of the transistor q5

    電平調節電路100將送往第一個時鐘終端ck1的時鐘信號從h電平降低一個預定值，並將此信號送往晶體管q5的輸入端。
  8. The counter has been preset to 0000 and as the input " runs, " the counter advances by 1 bit per input pulse

    計數器預置0000 ，並在時鐘輸入下計算每輸入一個脈沖計數器便累加10 。
  9. The concept of " timing " in the article is not the clock in our ordinary living, but syntheses which is made up of some frequency source in the signal generator ( such as cs atom frequency standard, rb clock & high accuracy quartz crystal oscillator ) which produces the primary frequency, the matching input interface and the matching output interface and controlling circuit etc. for example, bits is a kind of timing equipment, which is used to control the timing of some functions

    本文論及的「時鐘」概念不是指日常生活中使用的鐘表，而是由產生基準頻率的信號發生器（如銫原子頻率標準、銣鐘及高精度石英晶體振蕩器等）中的某種頻率源以及相配套的輸入、輸出介面和控制電路等組成的一整套具有特定同步定時功能的綜合體。如bits就是一種時鐘設備，它提供用在通信系統中控制某些功能的定時的時間基準設備，時鐘提供的信號稱為基準信號、定時信號或同步信號。
  10. Enter the amount of time, in integer minutes, after which the authentication cookie expires

    輸入以整數分鐘的時間量，超過此時間量，身份驗證cookie將過期。
  11. Plc, robot and cad / cam are called the three major pillars in the modem factory automation. plc, as the head of the three, has become the leading basic automatic equipment in the field of the industry control in the early 1980s " but as a matter of fact, plc being with the lack of friendly man machine interface, rnakes no close relationship between human and machineometimes it even can not be promoted and applied in some fields aiming at the situation mat those imported products are too expensive while domestic products are of rare famous brands, a plc man - machine interface - plc monitor is developedthis paper systemically introduces the developing procedure for the whole system, including how to design hardware and software system. especially emphasizing plc communication protocol. real time message accessing, lcd controller instruction set, definition of data construction for message & tag screens and how to display thern, assignment of internal resource of cpuealization in software among plc & manitor, file format defining a nd download of user data, etcplc monitor will compensate some weakpoints of plc, and extend the application rangeimultanneously enhance the performance of plc and increase the attached value of mechanical machines, undoubtedly it will see hight market prospect

    針對人機界面進口產品的高昂價格和國產品牌稀少的這一現狀，研製開發了一種plc人機界面? plc監控器。本文系統地介紹了整個系統的開發過程，包括硬體系統、軟體系統的設計及實現，重點介紹了plc通信協議，監控器的基本工作原理以及期望實現的功能，監控器電源電路、 sram存儲器掉電保護電路、 cpu監控器電路、按鍵輸入電路的設計及按鍵狀態的讀入，時鐘信息的設定與讀取， cpu液晶顯示器指令系統，信息畫面及標簽數據結構的定義及顯示方法， cpu內部資源的分配，監控器與plc通信的軟體實現，文件格式的定義以及畫面數據的下載等。 plc監控器彌補了plc一些方面的不足，可以擴大plc的應用范圍，提升機械設備的檔次，增加設備的附加價值，具有一定的市場前景。
  12. Pcb board is finished by using protell99se. power supply module, signal - sampling module, mcu, keyboard input, lcd module, and cpld are designed. the third chapter completes the software design and the debugging in keil environment

    然後利用protell99se平臺完成pcb圖的設計和制板工作，根據晶元資料設計出供電模塊，信號採集模塊，單片機系統，日歷時鐘晶元，鍵盤輸入，液晶顯示系統，可編程式控制制模塊和各個模塊間介面。
  13. Using an 8 - depth async fifo solves the synchronization and exchange of data be - tween different clock domains. the data transaction protocol comes from the most basic work way of uart. when the master clock is 16. 7mhz, the pcm side and adpcm side clocks both are 2. 38mhz, the results of simulation show that the latency from the start - bit of pcm data inputting uart receiver to the stop - bit of adpcm data outputted uart transmitter is 14. 3 us and the latency from the start - bit of adpcm data inputting uart receiver to the stop - bit of pcm data outputted uart transmitter is 14. 7 us

    在主時鐘為16 . 7mhz ， pcm數據端與adpcm數據端時鐘均為2 . 38mhz時，模擬結果表明從pcm的起始位輸入uart接收器到adpcm終止位輸出uart發送器的最大延遲為14 . 3 s ，從adpcm的起始位輸入uart的接收器到pcm終止位輸出uart發送器的最大延遲為14 . 7 s ，設計時盡可能的使編碼與解碼的時間相差不多，從結果看出基本達到這個要求。
  14. And the selection and design of switch - in module, switch - out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed

    論文中還給出了開關量輸入、開關量輸出、通信模塊、時鐘電路、數據存儲器、按鍵電路和頻率跟蹤電路等各功能模塊的選擇方法和設計原理。
  15. That easily saved a minute or more of typing for just one class

    對於一個類來說，這可以很輕松地節約一分鐘的時間，或者減少大量輸入工作。
  16. The whole pwm circuit contains two subcircuit, the front - end is pwm module that make up of the counter that based on nine mosfet true - single - phase - clock d flip - flop ; the back - end is demodulated module, which is consist of a three order chebyshev low - pass filter used trans - conductor capacitor. all the subcircuits are simulated. at last, an approving simulated result of the whole circuit is given too

    在調制部分，利用九管單相時鐘d觸發器構成計數器，並由此組成了脈沖寬度調制電路，同時給出了在典型溫度下的模擬結果;在解調部分，介紹了低通濾波器從無源到有源的設計方法，設計了三階切比雪夫低通跨導電容濾波器，同樣給出了相應的模擬結果;最後，作為將脈沖寬度調制電路和濾波器作為整體電路，以脈沖調頻波為輸入進行了模擬，取得了令人滿意的結果。
  17. Continuing, this paper has detailedly presented all writer have achieved works, which involve designing and implementing audio data assignment func tion, software on - line upgrade function, real time clock driver programme, user input process function, and testing the terminal ' s interoperability with some other h. 323 devices

    接著，介紹了作者完成的工作：設計實現了語音數據調度功能、軟體自更新功能、實時時鐘驅動程序和用戶輸入處理功能，以及終端與其它相關的h 323設備的互通測試。
  18. You can enter valid times using a 12 - hour or 24 - hour clock

    可以使用12小時或24小時時鐘輸入有效的時間。
  19. The periphery electric circuit of adc was designed, including 3 - wire serial port configuration circuit, analog input electric circuit, clock input circuit and power

    對adc的外圍電路進行設計，包括三線串口配置電路、模擬輸入電路、時鐘輸入電路和電源電路。
  20. For example, if it takes about 60 seconds for a user to enter all the information required for a web - based time - entry form, 60 seconds is the think time for this scenario

    例如，如果用戶花大約60秒鐘在基於web的時間輸入表單中輸入需要的所有信息，則此方案的思考時間是60秒。
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