時間寄存器 的英文怎麼說
中文拼音 [shíjiānjìcúnqì]
時間寄存器
英文
time register- 時 : shí]Ⅰ名1 (比較長的一段時間)time; times; days:當時at that time; in those days; 古時 ancient tim...
- 間 : 間Ⅰ名詞1 (中間) between; among 2 (一定的空間或時間里) with a definite time or space 3 (一間...
- 存 : 動詞1 (存在; 生存) exist; live; survive 2 (儲存; 保存) store; keep 3 (蓄積; 聚集) accumulat...
- 器 : 名詞1. (器具) implement; utensil; ware 2. (器官) organ 3. (度量; 才能) capacity; talent 4. (姓氏) a surname
- 時間 : time; hour; 北京時間十九點整19 hours beijing time; 上課時間school hours; 時間與空間 time and spac...
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On the base of analyzing the sparc instruction set, this paper researches the pipeline technology and the resolution of correlation problems, and these problems were resolved by using the harvard architecture, internal forwarding and delay branch technology
本文在分析sparc指令系統的基礎上,研究了流水技術及其相關問題的解決方法,並通過在硬體上使用哈佛結構、提前寫寄存器的操作時間以及內部前推和延遲轉移等技術較好的解決了結構相關、數據相關和轉移相關的問題。Memory management is simpler when all processes use the same segment register values when they share same set of linear addresses
當所有的進程都使用相同的段寄存器值時(當它們共享相同的線性地址空間時) ,內存管理更為簡單。The part of execution in which an operand or instruction is read from main stora ge and written into a control unit or arithmetic unit register
執行過程中的一個階段所需的時間,在此期間,計算機從主存儲器中取出指令或操作數,並將其存入控制器或運算器的寄存器中。For example, a compiler may choose to optimize a loop index variable by storing it in a register, or the cache may delay flushing a new value of a variable to main memory until a more opportune time
例如,編譯器為了優化一個循環索引變量,可能會選擇把它存儲到一個寄存器中,或者緩存會延遲到一個更適合的時間,才把一個新的變量值存入主存。Many traditional optimizations such as register allocation optimizations are able to reduce the energy consumption indirectly while reducing the executed instructions. for instance, the improvements to the code generation techniques for the register stack can reduce the register saves and restores, further reduce the energy consumption and the execution delay
例如在itanium中,對棧寄存器分配的優化,可以減少rse ( registerstackengine )的溢出和填入操作,從而減少了處理器的等待時間,同時,降低了指令執行帶來的功耗。This section addresses the timing relationships between transitions of one or more input signals that are necessary to ensure device functionality and applies only to sequential - logic devices ( e. g., flip - flops, latches, and registers )
本節為一個或更多輸入信號之間的時序關系提供尋址,這些輸入信號是使器件發揮作用的必須信號,並且只應用於順序邏輯器件(比如觸發器、鎖存寄存器和寄存器) 。A design method based on the decomposition and multiplexing technique of complex instruction, combined the decoding arithmetic of instruction and a step counter together, sub - step realization method of multiclocks is proposed. the similarities and differences of architecture between fsm and multi - ? ocks are discussed from two aspects, timing and state space
提出了執行周期復用的指令分解、指令寄存器與步長計數器聯合譯碼,以及多時鐘同步的控制流設計方法;進而從時間和狀態空間兩個角度深入討論了控制流設計中狀態機和多時鐘兩種常見體系結構的異同。The a / d and cap circuits on dsp sample the voltage and current signals coming from the signal sampling circuit and the speed signal of the motor respectively. the " dead time " register of the dsp prevent directive - through of the igbts on the up and the down bridge arms
利用dsp上的死區寄存器設置ipm驅動信號的死區時間防止上下橋臂igbt的直通;利用板上集成的a / d轉換器採集經過板級外圍電路處理的電路信號;利用板上的捕獲單元cap採集通過轉速計的輸出從而得到電機的轉速。分享友人