晶元尺寸 的英文怎麼說

中文拼音 [jīngyuánchǐcùn]
晶元尺寸 英文
csb :chiscale ball grid array
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 尺 : 尺名詞[音樂] （中國民族音樂音階上的一級 樂譜上用做記音符號 參看「工尺」） a note of the scale in ...
  • 寸 : Ⅰ量詞（長度單位） cun a unit of length （=1/3 decimetre）Ⅱ形容詞（極短或極小） very little; very ...
  1. During the course of the manufacture for packaging 2000 pixel hgcdte irfpa wafer, some crucial techniques are solved, such as the design of the button stem structures with inclined dragging wires applied in cryogenic platform, the optimization of long linear irfpa detector ' s signal wires layouts, the implement of a fanout board having thin film gold metalization for defining the required electrical conductors and a method of hermetically sealed vacuum enclosure of large dimension windows, etc

    在用於封裝2000元碲鎘汞焦平面晶元的分置式微型杜瓦研製中，詳細闡明了一種焦平面晶元其裝載面為斜拉式支撐結構的設計，實現了探測器外引功能線的布線優化及其輸出引線工藝改進，並提出了一種大尺寸高氣密光學窗口的焊接方法等關鍵技術。
  2. Testing of materials for semiconductor technology - determination of the geometric dimensions of semiconductor wafers - part 2 : testing of edge profile

    半導體工藝材料的試驗.半導體晶元幾何尺寸的測量.第2
  3. An automatic flip chip bonder is a precision instrument used to align and bond one or more dies onto a substrate in semiconductor industry. it develops for the mass production of ic, mems and moems with small feature sizes and high precise bonding demands. an alignment system is one of the key components in flip chip bonders

    全自動倒裝貼片機（ flipchipbonder ）是半導體生產工藝中完成晶元和基底對準、鍵合的高精度自動化設備，適合於特徵尺寸小，鍵合精度要求高的ic （ integratedcircuit ） 、 mems （ microelectromechanicalsystem ） 、 moems （ microopticalelectromechanicalsystems ）等的大規模生產。
  4. The type of packages and the methods in which it is possible to mount the finished semiconductor chip ( depending on factors such as heat dissipation, size, etc. )

    封裝的類型和方法（它們取決于熱耗散和尺寸大小等因素） ，用此種方式即可安置經過精製的半導體晶元。
  5. Ultrathin wafer level chip size package technology

    超薄型圓片級晶元尺寸封裝技術
  6. Along with silicon ulsi technology has seen an exponential improvement in virtually any figure of merit, as described by moore ’ s law ; the miniaturization of circuit elements down to the nanometer scale has resulted in structures which exhibt novel physical effects due to the emerging quantum mechanical nature of the electrons, the new devices take advantage of quantum mechanical phenomena that emerge on the nanometer scale, including the discreteness of electrons. laws of quantum mechanics and the limitations of fabrication may soon prevent further reduction in the size of today ’ s conventional field effect transistors ( fet ’ s )

    隨著超大規模集成電路的的發展，半導體硅技術非常好地遵循moore定理發展，電子器件的特徵尺寸越來越小;數字集成電路的晶元的集成度越來越高，電子器件由微米級進入納米級，量子效應對器件工作的影響變的越來越重要，尺寸小於10nm將出現一些如庫侖阻塞等新特性。量子效應將抑制傳統晶體管fet繼續按照以前的規律繼續減小。在這種情況下，宏觀的器件理論將被替代，可能需要採用新概念的晶體管結構。
  7. So in one hand it requires the wafer ' s diameter to be more large in order to enhance the productivity, and on the other hand it puts forward more strict requirement about the crystal perfection and electricity character. especially the electronic character and the equality of micro - area in the crystal wafer has become the key factor to determine whether the device can be made on it or not. so the resistivity measurement of micro - area become one most important procedure in the chip machining. to ensure the produce quality of chip and the perfect performance of final production, the four - probe testing technology need to be deeply studied

    圖形日益微細化，電路尺寸不斷縮小，目前ic製造以8英寸、 0 . 13 m為主，預計在2007年左右將以12英寸、 65nm為主，這一方面要求圓片直徑不斷增大以提高生產率，另一方面對晶體的完美性、機械及電特性也提出了更為嚴格的要求。特別是微區的電學特性及其均勻性已經成為決定將來器件性能優劣的關鍵因素。因此，微區電阻率的測試成為晶元加工之中的重要工序。
  8. His team ' s sensors are engineered at the nanoscale ? the size of molecules ? and are cheap because they ' re etched out of flakes of silicon, the stuff of computer chips and beaches

    這種傳感器的尺寸在毫微級分子大小而且很便宜，因為它們都是用硅元素薄片（計算機晶元和沙灘的組成成分）作出來的。
  9. The eutectic crystal al3fe often is " needle " shape or short line shape but the shape of primary crystal al3fe is relative to the adding amount of fe powder and the temperature of heat preservation stirring. while the adding amount of pure fe powder is few and the temperature of heat preservation stirring is higher than the temperature of liquidus of al - fe binary alloys equilibrium phase diagram, the reaction synthetical primary crystal al3fe exhibits short worm shape

    加入量少，保溫攪拌溫度在al - fe二元合金液相線以上，則形成的初晶al _ 3fe呈短蠕蟲狀； fe加入量大，保溫溫度在液相線以上，初晶al _ 3fe以平面方式生長，復合材料中的初晶al _ 3fe呈塊狀或粒狀，尺寸較大（ 10 m以下） 。
  10. Eventually, around the cusp of the 1980s and 90s, the relentless march of miniaturization approached sizes so small that the larger area of the slower fet - based chips could be filled with enough transistors to whomp the performance superiority of the bipolar model

    在20世紀80年代和90年代的早期，晶元的小型化已經使得晶元的尺寸非常之小，以至於更小的基於fet的晶元上可以留出更多的空間，可以放置更多的晶體管，從而實現遠遠高出二極體模型的性能。
  11. For the powder milled to amorphous state, because of its very fine structure, it is easy to occur phase transformation and has good size stability when sintered

    研磨到非晶態的粉末由於元素達到原子尺度混合，大大縮短了擴散距離，不僅易於發生固態相變，而且燒結體尺寸穩定性好。
  12. First of all, single port negative impedance oscillator is analyzed in the thesis. a design method of gunn diode vco is introduced and an vco chip using gunn diode is fabricated. the substrate of the vco chip is gaas with dimension of 4. 4mmx3. 9mm

    本文首先對單埠負阻振蕩器進行了分析，給出了gunn二極體負阻振蕩器的設計方法，設計出了一個變容管調諧平面微帶gunn二極體vco晶元，該晶元以gaas為襯底，尺寸為4 . 4mm 3 . 9mm 。
  13. With the development of microelectronic products ( integrated circuit, printed circuit board, etc ) directing to high density, thin separation and low defect ratio, its inspection requirement is higher on aspects of precision, efficiency, universal, and intelligence etc. therefore, this paper researched on the general key techniques in the field of microelectronic products vision inspection, covered the shortage of traditional inspection on aspects of fast and precision locating, image mosaic, and fine defect test, completed theory study on physical dimension and defect inspection of microelectronic products based on machine vision, developed the prototype and used lots of experiments to prove its correctness and feasibility

    隨著微電子產品（集成電路晶元、印刷電路板等）向著高密度、細間距和低缺陷方向發展，對其檢測技術在精密、高效、通用和智能化等方面提出了更高要求。由此，本文對微電子產品視覺檢測中的關鍵技術進行研究，彌補了傳統檢測在精確快速定位、圖像全景組合和精細缺陷檢測等方面的不足，最終完成基於機器視覺的微電子產品外形尺寸和缺陷檢測的理論研究和樣機研製，並進行了大量實驗證明其正確性和可行性，力圖為我國自主創新的微電子產品視覺檢測技術提供理論和實際借鑒。
  14. The evolution on particle morphology, microstructure, grain size and microstrain of the mixture of ti and al elemental powders during mm has been investigated. it was found that the nanocrystalline composite powders with extremely fine ti / al alternative lamellar structure ( lamella spacing about 0. 1 ~ 0. 5 m ) could be prepared by mm using proper processing parameters

    研究了ti 、 al單質元素混合粉在機械球磨過程中的顆粒形貌特徵、組織結構、晶粒尺寸以及微觀應變的變化規律，表明在適當的球磨工藝條件下可獲得具有極細層片間距（ 0 . 1 ~ 0 . 5 m ）的納米晶ti / al機械復合粉。
  15. At that scale, materials are measured in nanometers or billionths of a meter. ghasemi - nejhad said the nanotechnology field could allow for the building of ever smaller chips that would reduce the size and weight of computers while increasing their speed and memory

    卡西米-內哈德說，通過採用納米技術，科學家還能製造出體積更小運算速度更快容量更大的晶元，同時減小計算機的尺寸。
  16. As an advanced package, 3 - d stacked csp assembly provides significant size and performance advantages than traditional single chip package. meanwhile, high packaging density tends to generate more power in a package and cause serious thermal problem

    三維疊層晶元尺寸封裝（ stackedchipscalepackage ）是目前最先進的微電子封裝形式之一，具有體積小、重量輕、封裝效率高等特點。
  17. Ut - scsp ultra - thin - stacked chip size package

    超薄疊層晶元尺寸封裝
  18. Description of some of the expected future developments in time and frequency standards and distribution, including such topics as chip - scale atomic clocks ( size of a rice grain, powered by aa battery, potentially capable of low cost mass production )

    介紹一些未來可預期的時間頻率標準和發布技術的進展，包括諸如「晶元級的原子鐘」 （大米粒尺寸，由aa電池供電，具有低成本大批量生產潛力） 。
  19. According to process rules of the gaas mmic product line, we properly designed the circuit layout. in order to reduce the overall chip size, the transmission lines are folded with sufficient spacing to avoid interline coupling. the lange couplers are also folded to keep the 90 and 180 bits " sizes similar to other phase shift bits " sizes

    結合實際mmic工藝線，合理設計移相器電路版圖，折疊微帶線並留出足夠大的線間距，以避免線間寄生耦合的發生，並折疊蘭格耦合器使90和180移相位的尺寸與其它相位的晶元尺寸保持一致。
  20. This increase in chip size means that designs get more complicated because they must manipulate and hold larger systems called soc, or " system - on - chip ", designs

    晶元尺寸的增加意味著設計工作將變得更加復雜，因為他們必須操作、控制更大的系統（稱為soc或" system - on - chip "設計） 。
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