晶元布局 的英文怎麼說
中文拼音 [jīngyuánbùjú]
晶元布局
英文
chilayout-
Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout
本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally
首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。Based on this background and by the support of the project " the application of the computational intelligence in vlsi physical design " from sichuan science and technology bureau foundation, this dissertation is intended to develop a tabu search algorithm based on computational intelligence methodology for the placement of vlsi physical design
由此，基於四川省科技廳基金項目? ? 《計算智能在超大規模集成電路物理設計中的應用》 ，本文對計算智能演算法中的禁忌搜索演算法在vlsi電路晶元布局設計中的應用進行了一些研究。Then has analysed function 、 port joining 、 inside structure of every module, etc. in detail. using hardware description language to program for function implementation, after function simulation 、 synthesis 、 place and route 、 timing simulation and download, the design is implemented in the spartan 3 serial xc3s400 - 4pq208 chips of xilinx. all procedure of design is worked under the ise 6. 2 integrated environment
接著詳細分析了各模塊的功能、埠連接、內部結構等，並利用硬體描述語言編寫源代碼實現各模塊功能，經過功能模擬、綜合、布局布線、時序模擬、下載等一系列步驟，最終在xilinx的spartan3系列xc3s400 - 4pq208晶元上實現。Firstly a routing problem among transistor groups is brought forward. by analyzing the property of optimized rectangle steiner tree, an algorithm of approximate rectangle steiner tree construction is proposed. according to the mutual exclusion relationship among the net ports in the dvcs, the strategy for choosing connection ports is advanced
論文首先提出了晶體管群之間的線網布線問題，通過分析優化矩形斯坦納樹的性質，提出了一種符合宏單元布局特徵的近似矩形斯坦納樹構造演算法，同時針對晶體管群dvc內引線端點間走線互斥關系，提出斯坦納樹可選端點篩選策略。3. floorplan : it is very important to plan the power domain, place macro cell
3 .晶元布局對于整個設計流程至關重要，完成對電源規劃，擺放macro等工作。The paper is composed by three parts ; we ' ll introduce the background of ic design in the first part, which also covers the developing in domestic and foreign industry ; the whole flow of digital ic backend design will be presented detailed in the second part ; the last part will summarize the paper, as well as discuss the future work
這篇論文主要包括如下三個部分:第一部分為緒論，主要關于國內外行業相關背景，以及課題背景;第二部分為數字後端設計開發過程，分為設計的初始化，時序設置，晶元布局，標準單元擺放，時鐘樹綜合，繞線，物理驗證。分享友人