晶元編號 的英文怎麼說

中文拼音 [jīngyuánbiānháo]
晶元編號 英文
chip number
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 號 : 號Ⅰ名1 （名稱） name 2 （別號; 字） assumed name; alternative name3 （商店） business house 4 （...
  • 編號 : 1 （按順序編號數） number 2 （編定的號數） identifier; serial number; 編號次序 numeral order; 編...
  1. This dissertation is supported by the following projects : the project of " the development and commercial usage of embedded 32 - bit mcu " from mii and the project of " the development of security chip based on pci ip " from the institute of vlsi design, hefei university of technology

    本文基於國家信息產業部項目「嵌入式32位微處理器開發及產業化」 （項目編號：信運部[ 2001 ] 900號）和合肥工業大學微電子設計研究所承接的設計服務項目「 pci介面信息安全晶元開發」 。
  2. In all kinds of complicated network, oriented linking and unlinking, communication frequency resource is strained, and bandwith to transmitting audio frequency signal is too restricted, complicated and fluky, while audio frequency data exponential have been increased in the last several years. under the circumstances, based on the research of predecessor, this paper studies wavelet analysis ' s maths gist and practices significance on signal process, and puts forward a optimized wavelet package condensation arithmetic to process audio frequency data, which gives attention to coding efficiency, multirate and compression delay. simulation experiment on the arithmetic has been done by matlab

    針對無連接和面向連接的各種復雜網路環境下，通信頻帶資源緊張，音頻傳輸帶寬有限且復雜多變，而各種音頻數據又日益增多的局面，本文研究小波分析在信號處理方面的數學依據和在數據壓縮方面的實際意義，在前人不斷工作的基礎上，提出了一種優化小波包變換編碼方案用於音頻數據的壓縮演算法，兼考慮了編碼效率、多碼率和壓縮時延多個方面，並在matlab環境下做了模擬實驗，對各種音頻信號及多種小波函數做了模擬結果比較，實驗結果證明該演算法可以在一定計算復雜度下可以很好地改進壓縮效果，達到多碼率下實現實時編解碼的過程，在高速dsp晶元等硬體設備支持下，可以有效應用於實際復雜多變信源編碼。
  3. With the developing of vlsi in recent years, high function dsp has been produced ( such as tms320 series dsp produced by ti ) and their cost is dropping. thus, this established the foundation for making complex speech coder practical and producible. the paper researched and discussed the fix - point real implementation of g. 728 by dsp tms320c5402 chip

    但是，近幾年來，隨著大規模集成電路（ vlsi ）的發展，已生產出高性能數字信號處理晶元（例如ti的tms320系列dsp晶元） ，而且其成本在不斷降低，這就為復雜的語音編碼器的實用化和產品化奠定了基礎。
  4. By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument

    本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。
  5. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  6. A arming control system of synchronous fitting missle is brough forward in this paper of which the arming control unit composes of the high speed digital signal processing chip dsp and fpga, and has better performance in speed and precision

    本文提出了一種雙聯裝導彈瞄準系統，其瞄準控制部分由高速數字信號處理晶元dsp和現場可編程門陣列fpoa構成，使得整個系統在速度和精度方面都具有較好的性能。
  7. Once has the bandits and thieves to intrude guards against the place, the detector launches the wireless coded signal immediately, the networking center number which installs when is apart from defense area 150 meter within the main engine to send out the police whistle sound to report to the police immediately, reports to the police dials to establish in advance or reports to the police the telephone, the handset number, answers in the police telephone to return puts user pre - record to report to the police the pronunciation, long - distance reports to the police, simultaneously comes the real - time transmission through the internet to deploy troops for defense, to withdraw from a defended position, to report to the police and so on the condition, inquires the historic record through the computer network

    該系統還採用美國進口原裝晶元與先進的無線數字高頻技術微電腦cpu控制器主機組成。在防範地點安裝好主機后，並設置在布防狀態。一旦有盜賊闖入防範地點，探測器立刻發射無線編碼信號，安裝在距防區150米以內的主機立即發出警笛聲報警，報警時撥打預先設定的聯網中心號碼或報警電話手機號碼，接警電話里回放用戶預錄的報警語音，遠程報警，同時通過網際網路來實時傳遞布防撤防報警等狀態，通過電腦網路來查詢歷史記錄。
  8. The system is consist of the main data processing board which is based onthe fpga device and fast ethernet phyceiver rtl8201l and a - law pcm data encoder and decorder chip msm7702 - 3, and the dial - up and display board which is based on mcu. the main board would carry out the core task of data processing, such as voice data packing and unpacking, the ethernet frame processing, protocol processing, call processing, etc. the dial - up and display board would carry out the task of display the ip address which is input by consumer and status of network during talk period from the main board, and so on. in the paper the system of lan ip telephone and the tcp / ip protocol is introduced firstly, then the fpga device is stated. after that the fpga - based hardware scheme is introduced in detail in chapter four

    系統以altera公司的acex1k系列的fpga和快速以太網控制器rtl8201l和語音編解碼晶元msm7702 - 3為核心構建了數據處理主板和以單片機為控制器的撥號顯示子板組成。數據處理主板的核心任務，包括語音數據處理、以太網幀處理、協議處理、呼叫處理等。撥號顯示子板則完成通話前的顯示用戶所撥過的ip地址，通話期間網路狀態的顯示等等。
  9. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  10. Although there have been many application instances in the field of input / output device technology, we need an specific project and technology route aimed at an given application. in this thesis, we combine the introduction and analysis of relative technology to describe the accomplishment of a coordinate collecting device which is based on incremental rotary encoder. this device is an specific device applied to collect the corrdinate displacement of ground image ’ s three - dimensional model created by full digital photogrammetric station. cpld chip and vhdl are applied in this device to carry out the following work : phase control of the electrical pulse created by incremental rotary encoder, counting the number of electrical pulse, controling the state of signal processing circuit, exchanging data between this circuit and pci control

    本文結合相關技術的介紹和分析，描述了一個基於增量式旋轉編碼器的坐標參量採集介面卡的實現，此介面卡是一種用於採集全數字攝影測量系統地面影像模型坐標位移量的專用設備，該設備採用cpld器件和vhdl語言實現增量式旋轉編碼器的脈沖信號鑒相和計數、信號處理部分的狀態控制以及和pci總線晶元ch365之間的數據交換和通信功能，同時該設備的驅動程序基於wdm模式，並且配置有結構良好的動態鏈接庫程序作為系統軟體和驅動程序之間的數據和控制交互中間介面，能夠方便地運行在windows98 / 2000 / xp操作系統平臺上，具有實時性強、工作穩定、通用性較好和性價比高等特點。
  11. According to the request of this subject, we have developed the system hardware and software for the slave device and the inspection software running on the pc. in this paper all of the followings is illustrated detailedly, such as the research on the principles of measurement and its realization, three means of water - level measurement that are separately based on photo electricity coder, pressure sensor and potentiometer ; selection of the microchip, we choose an advanced integrated soc ( system on chip ) microchip c8051f021 as the main controller ; realization of signal sampling, processing and its conversion in the mcu ; application of high precision 16 bits adc cmos chip - - ad7705 in our system, designing its interface with the microchip and relevant program ; using a trickle charge timekeeping chip ds1302 in the system which can provide time norm and designing of its i / o interface and program ; additionally, a 4 ~ 20ma current output channel to provide system check - up using ad421. in the system, ad421, ad7705 and the microchip compose spi bus ; to communicate with the master pc, here we use two ways which are separately rs232 and rs485 ; moreover, there are alarm unit, keyboard unit, power supply inspection unit and voltage norm providing unit in the system

    針對研製任務的要求，課題期間研製了下位機系統硬體和軟體，開發了上位機監控軟體，其中所作的具體工作包括：測量原理的研究和在系統中的實現，在本次設計中用三種方法來進行水位測量，分別是旋轉編碼器法、液位壓力傳感器法和可變電阻器法；主控晶元的選擇，我們選用了高集成度的混合信號系統級晶元c8051f021 ；實現了信號的採集和處理，包括信號的轉換和在單片機內的運算；高集成度16位模數轉換晶元ad7705在系統中的應用，我們完成了它與單片機的介面設計及程序編制任務；精確時鐘晶元ds1302在系統中的應用，在此，我們實現了用單片機的i o口與ds1302的連接和在軟體中對時序的模擬，該晶元的應用給整臺儀器提供了時間基準，方便了儀器的使用；另外，針對研製任務的要求，還給系統加上了一路4 20ma模擬信號電流環的輸出電路來提供系統監測，該部分的實現是通過採用ad421晶元來完成的，本設計中完成了ad421與單片機的spi介面任務，協調了它與ad7705晶元和單片機共同構成的spi總線系統的關系，並完成了程序設計；與上位機的通信介面設計，該部分通過兩種方法實現： rs232通信方式和rs485通信方式；系統設計方面還包括報警電路設計、操作鍵盤設計、電源監控電路設計、電壓基準電路的設計。
  12. Pcb board is finished by using protell99se. power supply module, signal - sampling module, mcu, keyboard input, lcd module, and cpld are designed. the third chapter completes the software design and the debugging in keil environment

    然後利用protell99se平臺完成pcb圖的設計和制板工作，根據晶元資料設計出供電模塊，信號採集模塊，單片機系統，日歷時鐘晶元，鍵盤輸入，液晶顯示系統，可編程式控制制模塊和各個模塊間介面。
  13. It has application in dvd and htdv and dvb - c and video transmission in network, etc. two parts the principle of video reduced on mpeg - 2 standard and the designing of encoder and debugging on encoder are primarily expatiated on in this dissertation

    本文編碼器採用fujitsu公司的mpeg - 2編碼晶元mb86390用硬體來實現視頻信號的壓縮，編成mpeg - 2碼流，可應用於dvd 、數字電視、 dvb - c及視頻的網路傳輸等。
  14. This paper focuses on the research and implementation of these six key techniques. firstly, this paper researches the international standards for compression of digital video data, analyses how to compress analog video stream to mpeg - 4 with hardware. it is also involved in the techniques of net transmit of digital video data, such as net protocol, ip multicast, rtp / rtcp and so on

    本文主要是對智能視頻監控系統關鍵技術的研究與實現，主要體現在以下幾個方面: 1 、在視頻數據的壓縮方面，研究與分析了視頻壓縮的標準以及對mpeg - 4壓縮標準做了簡單的介紹，並分析了mpeg - 4的硬體實現方式，即使用硬體編碼晶元vw2010將視頻信號轉換為mpeg - 4格式的視頻流。
  15. Hence, the requirements of the servo control card are getting much sophisticated. in this thesis, the research work and implementation details of a 6 axes servo control card are discussed. this card is based on the ti company ? dsp chip tms320f240 and has realized the following functions : a ) signal encoder, b ) position limit, c ) dual ram communication with cpu, d ) coordinated control e ) dia conversion

    該卡以ti公司的16位定點數字信號處理器tms320f240為核心晶元，實現6路編碼器信號輸入處理，軸限位中斷處理，通過雙埠ram與pc進行通訊，接收pc發送過來的控制指令和數據，完成插補運算、聯動運算等控制，通過d / a轉換電路，將結果轉化為模擬電壓送伺服放大器驅動電機。
  16. And then, aiming at the deficiency of conventional design, the high - compositive fpga ( filed programmable gate array ) chip is used as the core in this project to deal with the signal of six encoders in real time

    其次針對以往設計的不足，採用了以高度集成的fpga （現場可編程邏輯陣列）晶元為核心的設計方式，實現六路光電編碼器信號的同步實時處理。
  17. 2. to implement the conversion of signal, a multi - channel time / data convert module with high precision and programmable time resolution is used. its characters and usages, including the theory and the software configuration program by using the chip sn74 | act8990, are introduced in the dissertation

    2 .為完成信號的轉換，儀器選用了一個多通道，高精度、具有可編程時間分辨能力的時間/數字變換模塊（ tdc ） ，論文介紹該模塊的特點，以及在課題中的使用方法，包括實現其軟體配置的晶元sn74act8990的原理和編程方法。
  18. On designing of the encoder, by using the decoding for video chip saa7113 made in philips, analog video signal inputted realizes a / d conversion in analog / power block

    編碼器的設計中，模擬/電源塊主要實現的功能是對輸入的模擬視頻信號進行a / d轉換，解碼晶元採用philips公司saa7113 。
  19. In hardware design, an integrated multi - center a / d chip is for input signal conversion, cpld and arm empu are the core of fault diagnosis system and information processing. host computer is connected with the system through network technology - which owns certain advantages such as wide range of input signal, powerful processing ability and low power consumption ; also it can be extended as a remote portable terminal

    在硬體設計上，採用集成多通道a / d轉換晶元完成輸入信號的轉換，使用大規模可編程邏輯器件和高性能嵌入式處理器作為故障診斷系統控制和信息處理的核心，採用網路技術實現診斷系統與主機的連接，系統具有前端輸入信號范圍寬，處理能力強，功耗低，可擴展為遠程診斷系統便攜式終端等優點。
  20. This makes wide - band digital receiver become a certain trend in the detecting and intercepting of radar signals field. in this dissertation, the parameter estimation algorithms for the monopulse signal, the linear frequency modulation signal and the phase coded signal are studied. according to the algorithms, a hardware platform is set up and tested using tms320c6713b mainly

    本文對單脈沖信號、線性調頻信號和相位編碼信號這三種常見的雷達信號的參數估計演算法作了研究和驗證，並根據這些演算法要求，立足於當前數字信號處理晶元（ dsp ）的發展，基於tms320c6713b構建了一個信號參數估計的硬體平臺。
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