晶體封裝 的英文怎麼說

中文拼音 [jīngtǐfēngzhuāng]
晶體封裝 英文
crystal packaging
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 體 : 體構詞成分。
  • 裝 : Ⅰ名詞1 （服裝） dress; outfit; attire; clothing 2 （演員的化裝品） stage makeup and costume Ⅱ動詞...
  • 晶體 : [晶體學] crystal; vitrella; crystal body; crystalloid; x-tal
  • 封裝 : [半] package; potting; encapsulation; enclosure; packing; cladding; jacketing; encapsulating; pac...
  1. The type of packages and the methods in which it is possible to mount the finished semiconductor chip ( depending on factors such as heat dissipation, size, etc. )

    封裝的類型和方法（它們取決于熱耗散和尺寸大小等因素） ，用此種方式即可安置經過精製的半導體晶元。
  2. Finite element method ( fem ) was used to simulate thermal and vibration problems in stacked - die csp assembly. finite element models and apdl programes were built in ansys to conduct thermal, thermal - mechanical and vibration analysis. the aim of these researches were trying to find some possible reasons and trends which affect the reliability of stacked csp / bga assembly and give some useful suggestions for the packaging design

    本論文正是針對以上情況，以採用引線鍵合工藝的三維疊層csp / bga封裝（裸晶元疊裝）為研究對象，在有限元分析軟體ansys中建立相關的有限元模型，編制了相應的apdl參數化分析程序，進行了溫度場分析、熱循環加載下的snpb合金焊點疲勞分析和實裝pcb板的振動模態分析。
  3. With the existing condition, the bar waveguide on the lithium niobate wafer with liquid phase proton - exchanged method has been fabricated and the benzoic acid is used as the proton source. a series of research on the domain inversion in lithium niobate crystal with proton - exchanged method have been done. and then the operation and the process of domain inversion in lithium niobate crystal with proton - exchanged method has been used

    實驗方面，利用實驗室現有條件，在鈮酸鋰晶片上以苯甲酸為質子源，用液相質子交換法製作了條形波導;對用質子交換法實現鈮酸鋰晶體疇反轉進行了一系列實驗研究，在此基礎上提出了質子交換法實現鈮酸鋰晶體疇反轉的工藝過程，實現了疇反轉並腐蝕得到了v型槽;設計製作了帶尾纖的電光相位調制器，最後進行封裝。
  4. For designing the microwave power amplifier formed by the chip of sige hbt more accurately, an novel method to extract chip s - parameter from s - parameter of packaged device with package is proposed

    為了更精確設計由sige異質結晶體管（ hbt ）管芯構成的微波功率放大器，本論文提出了一種新穎的從管殼封裝器件的s參數中提取出管芯s參數方法。
  5. Thermal and welding residual stress often produces in the proceeding of the electronic package, the residual stress release and thermal deformations of the microelectronics will reduce the assemble intensity between the chip and package, and then debase the electrical performance of the assemble circuit, numerous thermal cycling will lead to thermal fatigue or thermal failure of the microelectronics

    電子封裝器件在生產的工藝過程中，往往會產生熱殘余應力以及焊接殘余應力，殘余應力的釋放作用及器件在使用過程中的熱變形，會降低集成電路晶元與封裝體的結合強度，進而降低集成電路的電性能，反復的熱循環，將導致器件的熱疲勞失效，嚴重時可導致矽片或陶瓷片破裂，使整個器件遭到破壞。
  6. Bipolar transistors of the type of 3dd820 and 3dd15d ( with f2 metal - pack ) are taken as an example in the study to verify the method of controllable junction temperature

    以3dd820 ， 3dd15d （ f2金屬封裝）雙極晶體管為實驗對象，對結溫可控的晶體管穩態工作壽命試驗方法進行了驗證。
  7. At every step of production, from crystal growth to device packaging, numerous refinements are being made to improve the yield and reliability.

    在生產中，為提高其成品率和可靠性，從晶體生長到器件封裝每一步工序均有很多細致工作要做。
  8. Bsp supplies the simple interface to operate the peripheral chips conveniently. thus, real - time operating system ( rtos ) can start up from the various hardware successfully and response to the asynchronous event opportunely. on the other hand, rsp implements the encapsulation to rtos and brings up the process model according to the running character of the business layer, realizes the secondary process schedule inside task

    一方面，支撐子系統bsp層（板級支撐包）的設計實現了對硬體層的封裝，這包括對cpu （ mpc8241 ）的封裝和對外部晶元（串口、網口等）的封裝，通過這層封裝使得實時操作系統能夠成功啟動，及時響應異步事件，實現了硬體的基本功能，並且為上層提供了簡單易用的操作晶元的介面，隔離了軟體對硬體功能要求所必需的具體細節。
  9. The hardware and software structure is set up through establishing the model of the pc - based cnc system. and by object oriented technology, the software ics of module are encapsuled based rtlinux system. all these realized the open architecture of the cnc

    通過建立基於pc的cnc系統模型，確定了系統的軟硬體結構；利用面向對象技術基於rtlinux將數控系統各功能模塊封裝成軟體晶元，初步實現了數控系統的開放性。
  10. The transistor count is 3. 8 million ; the package is surface mount 240 - pin quad flat pack ( qfp240 ) ; and the die size is 98mm2 ; the most advanced research progress on microprocessor architecture is extensively studied to get technical preparations for microprocessor design

    該處理器目前正在進行後端設計，即將採用0 . 25 mcmos工藝流片，整個處理器的晶體管數目為380萬，封裝形式是qfp240 ， die面積為98mm ~ 2 。
  11. Detail specification for low power silicon n - p - n switching transistors - 65 v, planar epitaxial, ambient rated, hermetic encapsulation - full plus additional assessment level

    小功率硅p - n - p型開關晶體管詳細規范. 65v平面外延額定環境條件密封封裝.全面附加評定級
  12. Resonant pressure sensors are fabricated by ic process and mems technology and bonded to a stress isolating mechanical structure and sealed into an evacuated package

    晶元利用半導體ic工藝和mems工藝製作，採用一種減小封裝應力的結構，完成壓力傳感器的真空密封及封裝。
  13. Gfm series solar modules are made of high efficiency solar cells in series or in parallel, high transmission rate and low iron tempered glass, anti - aging eva and high flame resistant tpt by hotlamination, with andized aluminum alloy frame. products have high efficiency, long life, easy installation, high resistance against wind pressure and hail impact etc advantages

    Gfm系列太陽能電池組件由高效晶體硅電池片串並聯，用高透光率低鐵鋼化玻璃、抗老化eva和優良的耐火性tpt熱壓密封而成，外加陽極化優質鋁合金邊框，具有效率高、壽命長、安裝方便、抗風、抗冰雹能力強的特性。
  14. As an advanced package, 3 - d stacked csp assembly provides significant size and performance advantages than traditional single chip package. meanwhile, high packaging density tends to generate more power in a package and cause serious thermal problem

    三維疊層晶元尺寸封裝（ stackedchipscalepackage ）是目前最先進的微電子封裝形式之一，具有體積小、重量輕、封裝效率高等特點。
  15. Transistor electromagnetic induction aluminium foil sealer is a new type of container sealing equip, which is manufactured by bringing in the most advanced us transistor power module and with main elements and parts employed in original packing abroad

    晶體管電磁感應鋁箔封口機系列是新一代的容器封口設備。選用美國最先進的晶體管功率模塊，主要元器件原裝進口。
  16. . detail specification for low power silicon n - p - n switching transistors - 20 v, planar epitaxial, ambient rated, hermetic encapsulation long lead version - full plus additional assessment level

    小功率硅n - p - n型開關晶體管詳細規范. 20v平面外延額定環境條件密封封裝
  17. . detail specification for low power silicon p - n - p switching transistors - 65 v, planar epitaxial, ambient rated, hermetic encapsulation long lead version - full plus additional assessment level

    小功率硅p - n - p型開關晶體管詳細規范. 65v平面外延額定環境條件密封封裝
  18. To research the power consumption of gas sensors, often the front - side of the sensor array has fabricated, the back - side of the sensor is etched to form an air gap between substrate and housing

    為了研製低功耗氣體傳感器，在傳感器陣列上表面制備完成後，從下表面腐蝕傳感器晶元的基底，以造成傳感器晶元和封裝室之間形成一個空氣夾層。
  19. Detail specification for low power silicon p - n - p switching transistors - 65 v, planar epitaxial, ambient rated, hermetic encapsulation - full plus additional assessment level

    小功率硅p - n - p型開關晶體管詳細規范. 65v平面外延額定環境條件密封封裝全面附加評定級
  20. Detail specification for low power silicon p - n - p switching transistors - 25 v, planar epitaxial, ambient rated, hermetic encapsulation - full plus additional assessment level

    小功率硅p - n - p型開關晶體管詳細規范. 25v平面外延額定環境條件密封封裝全面附加評定級
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