晶體管化的 的英文怎麼說

中文拼音 [jīngtǐguǎnhuàde]
晶體管化的 英文
transistored
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 體 : 體構詞成分。
  • 管 : Ⅰ名詞1 （管子） pipe; tube 2 （吹奏的樂器） wind musical instrument 3 （形狀似管的電器件） valve;...
  • 的 : 4次方是 The fourth power of 2 is direction
  • 晶體 : [晶體學] crystal; vitrella; crystal body; crystalloid; x-tal
  1. It ' s a nation of some 200 million transistorized, deodorized

    這是一個2億多晶體管化的
  2. It ' s a nation of some 200 million transistorized, deodorized.

    這是一個2億多晶體管化的. .
  3. In the entitative routing stage, the macro - cell layout must be compressed for optimization area and time delay. it should be compared beauty with the routing result by manual. an algorithm, which is gridless, variable widths and minimizing layer permutation, is advanced for channel region

    晶體管級實體布線階段，由於庫單元的復用性，要求庫單元版圖緊湊，即要求單元版圖在滿足各約束條件的前提下面積、性能優化程度較高，能與手工設計的版圖相媲美。
  4. Standard test method for separating an ionizing radiation - induced mosfet threshold voltage shift into components due to oxide trapped holes and interface states using the subthreshold current - voltage characteristics

    利用亞閾值安伏特性測定由於氧化空穴和界面態產生的電離輻射感應金屬氧化物半導體場效應晶體管閾電壓偏移分量的標準試驗方法
  5. With recent improvements in transistorized circuits, the range is being constantly improved.

    近年來隨著電路晶體管化的改進，限度正不斷改善。
  6. Railway rolling stock. functional general requirements. transistorized ballasts. collection of particular leaves

    鐵路機車車輛.一般功能要求.晶體管化鎮流器.特殊葉片間的聯系
  7. Device degradation behaviors of typical - sized n - type metal induced lateral crystallized polycrystalline silicon thin film transistors were investigated under two kinds of dc bias stresses : hot carrier stress and self - heating stress

    本文主要研究了典型尺寸的n型金屬誘導橫向結晶多晶硅薄膜晶體管在兩種常見的直流應力偏置下的退化現象:熱載流子退化和自加熱退化。
  8. The trained neural network model can be used to solve a variety of problems emerged in rf / microwave circuit design, such as in microwave circuit cad, the established model structure can be used to characterize the nonlinear behavior of microwave circuits

    如用於微波電路cad ，可用所建立的模型結構來描述這么一類微波電路的非線性行為特徵；如用於微波電路設計，則可進行如共面波導、晶體管、傳輸線、濾波器和放大器等的設計；如用於微波電路優化，則可用所建立的電路模型優化電路參數，進行阻抗匹配等。
  9. During this precess, using the technology of optimizing the widths of both common source mosfet and common gate mosfet under a fixed power, we obtained a compromised result of power consumption and noise figure

    設計過程中，在限定功耗的前提下，主要針對共源晶體管和共柵晶體管的柵寬，對電路的性能進行了優化，使得設計的lna的噪聲系數最小。
  10. Abstract : a vertical sandwich deep trench with a field limiting ring is proposed to improve the breakdown voltage of power devices and high voltage devices. simulation result shows that nearly 100 breakdown voltage of the plane junction can be realized

    文摘:提出一種二氧化硅/多晶硅/二氧化硅夾心深槽場限制環新結構來提高晶體管的擊穿電壓.模擬結果顯示，該結構可以使射頻功率雙極性晶體管的擊穿電壓幾乎100達到平行平面結的理想值
  11. Discrete semiconductor devices - metal - oxide semiconductor field - effect transistors mosfets for power switching applications

    半導體分立器件.電力開關設備的金屬氧化物半導體場效應晶體管
  12. Wirings of the poly layer are always utilized under the silicon grid technics. to control the macro - cell signal delay and improve signal integrality, the crossing among different nets must be averagely distributed to reduce the number of layer permutation. the metal layer wirings should be maximized and the length of poly layer wiring in each net should be minimized

    硅柵工藝晶體管級布線利用多晶層走線，為了控制宏單元時延性能及改善信號完整性形態，關鍵是不同線網間交叉的均衡分配以減少走線的換層次數，最大化金屬層走線以及每一線網多晶層走線長度的有效控制。
  13. After constructing a 35 - nanometer - high channel between two silica plates and filling it with potassium chloride saltwater, they demonstrated that voltage applied across this nanofluidic transistor could switch potassium ion flow on and off

    他們在兩片硅板之間製作35奈米高的通道，注入氯化鉀溶液，示範在這個奈米流體晶體管上施加的電壓可開啟或阻斷鉀離子流。
  14. Xing su ( microelectronics and solid state electronics ) directed by prof. lin chenlu the fast development of information technology requires integrated circuit to be greater integrated, faster functioned, and lower power - consumed, that lead to continuous shrinkage of mos and dram feature size. and under this trend the thickness of mos gate dielectrics ( sio2 ) would soon scale down to its physical limit

    日益增長的信息技術對更高集成度、高速、低功耗集成電路的需求，驅使晶體管的尺寸越來越小，隨之而來的問題是作為mos柵氧化物和dram電容介質的sio _ 2迅速減薄，直逼其物理極限。
  15. It is found that the current amplification coefficient strongly depends on the spin polarization of the electrons injected from the emitter to the base, the spin relaxation time and the width of the base

    自旋晶體管中的電流放大系數主要取決于注入基區的自旋極化電子的極化程度，基區中自旋的馳豫時間及基區的寬度。
  16. In the paper, an automatic macro - cell routing system, which bases on the architecture of three levels : chip, macro - cell and transistor group, is discussed

    本文基於晶元、宏單元、晶體管群三級的層次化架構，實現了一個宏單元自動布線系統。
  17. Eventually, around the cusp of the 1980s and 90s, the relentless march of miniaturization approached sizes so small that the larger area of the slower fet - based chips could be filled with enough transistors to whomp the performance superiority of the bipolar model

    在20世紀80年代和90年代的早期，晶元的小型化已經使得晶元的尺寸非常之小，以至於更小的基於fet的晶元上可以留出更多的空間，可以放置更多的晶體管，從而實現遠遠高出二極體模型的性能。
  18. Most drive systems offer a choice between transistorized silicone - controlled rectifiers and pulse width modulation over the full range of amplified voltages

    大多數驅動系統提供兩個調節全程放大電壓的選擇：晶體管化的硅樹脂控制整流器和脈沖寬度調制器。
  19. Compared with the similar research results, the weighted control ic here has the following characteristics : ( 1 ) the circuit structure is simpler ; ( 2 ) the chip ' s fabrication is compatible with standard cmos process ; ( 3 ) n - mosfets with high w / l ratio and short channels are used for weighting and output to reduce the insertion loss ; ( 4 ) the weighting factor varies in a relatively wide range with the controlling signals ; ( 5 ) input and output impedance approach 50 in low frequency ( e. g. 50mhz ), while in higher frequency they slightly deviate from 50, hence the energy reflection lower than 0. 1 ; ( 6 ) it completes the functions of sampling, weighting, controlling and summing of high frequency analog signals

    它的加權控制電路與已報道的相關電路相比具有如下特點：電路結構簡單；製造工藝與普通cmos工藝兼容：短溝道，高寬長比的nmos晶體管具有低的通導電阻，將其作為加權、輸出器件可降低由電路引起的插入損耗；改變加權信號，可實現權值在較大范圍內的連續變化；輸入、輸出阻抗在低頻（如50mhz ）下接近50 ，而在高頻下略有偏離50 ，但反射系數均低於0 . 1 ；實現了對高頻信號的取樣、加權、控制、疊加功能的迭加。
  20. Poly - crystallization silicon thin film transistor ( p - si tft ) addressing liquid crystal display has been currently the research and development focus in the field of flat panel displays, as it is most feasible approach to high resolution, high integration and low power consumption as a result of its high aperture ration. there are less number interface of the crystal grain, lower metal impurity and higher mobility in the electric current director, the milc p - si tft has been the research focus in the fields of amlcd, projection display, oled etc. there are vast dangling bonds and bug

    多晶硅薄膜晶體管（ p - sitft ）液晶顯示器可以實現高解析度、高集成度、同時有效降低顯示器的功耗，因而成為目前平板顯示領域主要研究方向;而以橫向晶化多晶硅為有源層的tft由於在導電方向有更少的晶界、更低的金屬雜質污染、更高的載流子遷移率而成為目前有源矩陣液晶顯示領域、投影顯示、 oled顯示等領域研究的熱點。
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