晶體管級硅 的英文怎麼說

中文拼音 [jīngtǐguǎnjíguī]
晶體管級硅 英文
transistor grade silicon
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 體 : 體構詞成分。
  • 管 : Ⅰ名詞1 （管子） pipe; tube 2 （吹奏的樂器） wind musical instrument 3 （形狀似管的電器件） valve;...
  • 級 : Ⅰ名詞1 （等級） level; rank; grade 2 （年級） any of the yearly divisions of a school course; gra...
  • 硅 : 名詞[化學] silicon （14號元素符號 si）
  • 晶體 : [晶體學] crystal; vitrella; crystal body; crystalloid; x-tal
  1. Semiconductor discrete device. detail specification for pnp silicon low - power transistor for type 3cg110gp gt and gct classes

    半導體分立器件gp gt和gct級3cg110型pnp硅小功率晶體管.詳細規范
  2. Semiconductor discrete device. detail specification for npn silicon high - frequency low - power transistor for type 3dg130gp gt and gct classes

    半導體分立器件gp gt和gct級3dg130型npn硅高頻小功率晶體管.詳細規范
  3. Semiconductor discrete device. detail specification for npn silicon low - power hiht - reverse - voltage transistor for type 3dg182gp gt and gct classes

    半導體分立器件gp gt和gct級3dg182型npn硅小功率高反壓晶體管.詳細規范
  4. Wirings of the poly layer are always utilized under the silicon grid technics. to control the macro - cell signal delay and improve signal integrality, the crossing among different nets must be averagely distributed to reduce the number of layer permutation. the metal layer wirings should be maximized and the length of poly layer wiring in each net should be minimized

    硅柵工藝晶體管級布線利用多晶層走線，為了控制宏單元時延性能及改善信號完整性形態，關鍵是不同線網間交叉的均衡分配以減少走線的換層次數，最大化金屬層走線以及每一線網多晶層走線長度的有效控制。
  5. Along with silicon ulsi technology has seen an exponential improvement in virtually any figure of merit, as described by moore ’ s law ; the miniaturization of circuit elements down to the nanometer scale has resulted in structures which exhibt novel physical effects due to the emerging quantum mechanical nature of the electrons, the new devices take advantage of quantum mechanical phenomena that emerge on the nanometer scale, including the discreteness of electrons. laws of quantum mechanics and the limitations of fabrication may soon prevent further reduction in the size of today ’ s conventional field effect transistors ( fet ’ s )

    隨著超大規模集成電路的的發展，半導體硅技術非常好地遵循moore定理發展，電子器件的特徵尺寸越來越小;數字集成電路的晶元的集成度越來越高，電子器件由微米級進入納米級，量子效應對器件工作的影響變的越來越重要，尺寸小於10nm將出現一些如庫侖阻塞等新特性。量子效應將抑制傳統晶體管fet繼續按照以前的規律繼續減小。在這種情況下，宏觀的器件理論將被替代，可能需要採用新概念的晶體管結構。
  6. Semiconductor discrete device. detail specification for silicon n - channel deplition mode field - effect transistor of type cs1 gp, gt and gct classes

    半導體分立器件gp gt和gct級cs1型硅n溝道耗盡型場效應晶體管.詳細規范
  7. Semiconductor discrete device. detail specification for silicon n - channel deplition mode field - effect transistor of type cs4. gp, gt and gct classes

    半導體分立器件gp gt和gct級cs4型硅n溝道耗盡型場效應晶體管.詳細規范
  8. Semiconductor discrete device. detail specification for silicon n - channel deplition mode field - effect transistor of type cs10. gp, gt and gct classes

    半導體分立器件gp gt和gct級cs10型硅n溝道耗盡型場效應晶體管.詳細規范
  9. Detail specification for low power silicon n - p - n switching transistors - 65 v, planar epitaxial, ambient rated, hermetic encapsulation - full plus additional assessment level

    小功率硅p - n - p型開關晶體管詳細規范. 65v平面外延額定環境條件密封封裝.全面附加評定級
  10. Detail specification for low power silicon p - n - p switching transistors - 65 v, planar epitaxial, ambient rated, hermetic encapsulation - full plus additional assessment level

    小功率硅p - n - p型開關晶體管詳細規范. 65v平面外延額定環境條件密封封裝全面附加評定級
  11. Detail specification for low power silicon p - n - p switching transistors - 25 v, planar epitaxial, ambient rated, hermetic encapsulation - full plus additional assessment level

    小功率硅p - n - p型開關晶體管詳細規范. 25v平面外延額定環境條件密封封裝全面附加評定級
  12. Detail specification for low power silicon n - p - n switching transistors - 20 v, planar epitaxial, ambient rated, hermetic encapsulation - full plus additional assessment level

    小功率硅n - p - n型開關晶體管詳細規范. 20v平面外延額定環境條件密封封裝.全面附加評定級
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