法器 的英文怎麼說

中文拼音 [fǎqì]
法器 英文
[宗教] musical instruments used in a buddhist or taoist mass
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  1. This process requires that the adder used in multibit addition handle three inputs.

    這就要求用於多位數相加的加法器具有三個輸入端。
  2. The concept used is that the bits of the two numbers to be added are made available to the adder synchronously.

    所用的方法是，將相加兩數的各位同步地輸入到加法器中。
  3. 5 knowles s. a family of adders. in proc

    本文設計實現了一種64位新型并行加法器。
  4. Chapter 3 introduces the correcting ability of the rs code. then it particularly states the definition and algorithm of galois field, and analyses the realization of the limited field multiplier based on the dual basis

    第三章分析討論了rs碼的特點，給出了伽羅華有限域的定義與運算規則，推導和分析了基於對偶基的有限域乘法器實現方法。
  5. Then we show an algorithm design of the elliptic curve crypto based on galois field. as a main part, the design theory and concrete solution of it are presented step by step, ic chip design method for implementation of the algorithm is described in detail

    設計完成了一種基於有限域的橢圓曲線加密演算法，主要包括適合於168bit橢圓曲線加密的有限域乘法、加法、除法器的實現； 4
  6. Today very accurate integrated circuit multipliers are available.

    目前，非常精確的集成電路乘法器已被採用。
  7. In addition, many other problems also exist in hardware neural network, including error problem, learning mode, parallel architecture, and also neural network inner linking problem, hidden layer and the realization of the multiplicator and etc. for instance, error problem : hardware neural network employs the limited precision, and will inevitably bring limited precision error

    另外，硬體實現神經網路還存在誤差問題，學習方式，并行結構等方面的問題，還有神經網路內部的連接問題，隱層及乘法器的實現等等。如誤差問題，硬體實現神經網路使用的是有限精度，不可避免的會產生有限精度誤差，選取合適的精度，才能既適合空間的要求，又避免對網路的實現產生一定的影響。
  8. Design of a parameterized floating point multiplier

    一種浮點乘法器的參數化設計
  9. As the core of the optical processor, optical vector - matrix multiplier ( vmm ) is a basic optical device of the optical computer

    光學矢量-矩陣乘法器是光計算機中最基本的一種功能部件。
  10. Design of a multiplier in an 8 - bit risc single - chip microcomputer

    結構單片機乘法器
  11. Binary algebraic adder

    二進制代數加法器
  12. One that adds, especially a computational device that performs arithmetic addition

    加法器，相加器相加物，尤指執行算術加法的計算器
  13. This algorithm is based on the 16 - fft about square root decomposition, and using the phase revolution unit replaces multiplication, and uses the serial butterfly operation unit. at last, gives the correspond realization measure in fpga

    本文根據一種基於平方根分解的16點fft演算法，採用相位旋轉因子取代乘法器，並利用串列流水蝴蝶運算單元給出了一種新的實現演算法，並介紹了其在fpga中相應的實現方法。
  14. 2. the add operation optical channel that can fulfill standing carry was set up, which solved the problem of uncertain carry - delay encountered in huge - numeral add operation with common successive earn

    2 、創建了「進位直達」加法器原理光路，解決了巨位數加法運算串列進位的不定長延時難題。
  15. Fire hazard testing - test flames - needle - flame test method - apparatus, confirmatory test arrangement and guidance

    著火危險試驗.試驗火焰.針狀火焰試驗方法.器具驗證性試驗設備和指南
  16. The data and conclusions prove that these designs are better than the original ones ; the floating - point adder is really optimized

    實驗證明這些設計的性能都比原有設計有所提高，達到了優化浮點加法器的目的。
  17. The main research area is the structure optimization of floating - point adder, which is intent to minimize the delay of floating - point addition and optimize the circuit structure

    主要研究方向是優化浮點加法器結構，減小浮點加法運算的延遲，優化電路結構。
  18. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  19. The subject inducts digital time division technology ( pwm ), which is more advantageous at the accuracy and the predigest of hardware than simulant multiplication. what they call measuring power energy reasonably is that measuting except harmonics power energy fed back power. yet it realizes reasonable measurement of power energy which measures by base wave ac parameters method base on digital time division

    本課題引入了數字時分割（ pwm ）脈寬調制技術，在測量的準確性、硬體電路的簡化等方面都比模擬乘法器具有較高的優越性。所謂合理的計量電能，就是不計非線性負載回饋給電網的負的諧波電能，而採用基於數字時分割的基波交流參數測量的方法，真正實現了電能的合理計量。
  20. It is designed for embedded applications with the following features : separate instruction and data caches ( harvard architecture ), 5 - stage pipeline, hardware multiplier and divider, interrupt controller, 16 - bit i / o port and a flexible memory controller. new modules can easily be added using the on - chip amba ahb / apb buses. it has flexible peripheral interfaces, so can be used as an independent processor in the board - level application or as a core in the asic design

    它遵照ieee - 1745 （ sparcv8 ）的結構，針對嵌入式應用具有以下特點：採用分離的指令和數據cache （哈佛結構） ，五級流水，硬體乘法器和除法器，中斷控制器， 16位的i / o埠和靈活的內存控制器，具有較強的異常處理功能，新模塊可以輕松的通過片上的ambaahb / apb總線添加。
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