浮點加法器 的英文怎麼說

中文拼音 [fúdiǎnjiāfǎqì]
浮點加法器 英文
floating point adder
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 浮點 : [計算機] floating decimal; floating point
  • 法器 : [宗教] musical instruments used in a buddhist or taoist mass
  1. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  2. The data and conclusions prove that these designs are better than the original ones ; the floating - point adder is really optimized

    實驗證明這些設計的性能都比原有設計有所提高，達到了優化浮點加法器的目的。
  3. The main research area is the structure optimization of floating - point adder, which is intent to minimize the delay of floating - point addition and optimize the circuit structure

    主要研究方向是優化浮點加法器結構，減小浮點加法運算的延遲，優化電路結構。
  4. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  5. This article deals with the method to determine the guard digit in the left normatlization of float point number in the analysis and design of computer system, and briefly introduces its application in practice

    摘要介紹了在計算機系統分析和設計中，用於浮點數左規格化的警戒位的設置方法，並簡要說明了該類警戒位與用於舍入的警戒位共同組成了運算器中的累加器的實際警戒位字長。
  6. The author is absorbed in research on technology of coprocessor design. in the floating - point addition the paper proposes a carry chain of dynamic and static mixed circuits and a good balance between speed and area of predicting leading - zero logic circuits, considering algorithm and construction of logic circuits. an approach of micro program controller design for coprocessor is put forward and a test bench is given to verify its function

    筆者研究協處理器的設計技術，在浮點加法器中提出動態與靜態結合設計進位鏈的方案以及前導零預測面積與速度的折衷方法；在微程序控制器的設計中提出一種協處理器微程序控制器的設計方法，並且給出其功能驗證的測試平臺。
  7. The product rule is very simple and easy to implement, and it does n ' t increase additional delay

    該「產生式規則」簡單而易以實現，而且不增加浮點加法器的延遲。
  8. The primary contents and innovations of this article are introduced below. in order to take advantage of the high speed of calculation, and at the same time, improve the accuracy and dynamic - range of the algorithm, three kinds of multi - input floating point adder algorithm ( fpa ) are summarized and a high - performance multi - input fpa structure is put forward with a self - defined floating point format. the performance of the high - performance structure on calculation speed and logic resource consuming is better than the normal structure

    論文的主要工作及創新點如下:為了充分利用fpga處理速度快的特點，同時盡量提高演算法的精度及動態范圍，本文在對浮點加法器演算法進行深入研究的基礎上，規納總結了三種不同的多輸入浮點加法器演算法，並創造性地提出了一種高效的多輸入浮點加法器結構及一種適合於fpga實現的自定義浮點數格式，這種高效的結構在所需的邏輯資源和運算速度上均遠優于傳統的多輸入結構。
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