浮點基 的英文怎麼說

中文拼音 [fúdiǎnjī]
浮點基 英文
floating-point basis
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 浮點 : [計算機] floating decimal; floating point
  1. In digital relay, the percentage of noise will increase rapidly with the increase of sampling rate when derivation calculus is substituted by sampled difference term. to solve this problem, a new method using fragment function integrated with the least square algorithm is proposed in this paper. the influence of white noise is greatly reduced and the accuracy of the dead angle calculation is nicely improved after adopting the new method

    在數字式保護中，如果用差分代替求導將導致噪聲的百分比誤差隨著采樣頻率的提高而劇增，本文對此進行了分析並提出了用分段樣條函數最小二乘法來計算電流波形的導數值，以便在提高采樣率的同時降低噪聲誤差的影響，並將其應用於基於32位浮點dsp的新型變壓器保護裝置。
  2. The development of single chips and analyzers at home and that of overseas compared, a kind of pocketable dual - channel and multi - function signal analyzer, based on dsp, are researched with the functions of dynamic analyzer, data logging acquisitor, start - up / coast - down analyzer and dynamic balancer, etc. and the functions data acquisition, storage, display and analysis of vibration signal are validated in practice, high - speed float point data calculation ability, large memory space and simple operation are the characteristics

    高性能單片機尤其是dsp功能晶元的採用及用戶技術要求的不斷提高，使得信號分析儀的功能越來越完善，在比較了國內外單片機和信號分析儀的發展現狀后，開發研製了一種基於浮點dsp晶元tms320c32的便攜式雙通道多功能信號分析儀，兼有動態信號分析儀、巡檢數采器、起停車分析儀、動平衡儀等多種儀器的功能。
  3. In this paper, a lot of researches and exploration are applied to studying the universality and expansibility of hardware and the arithmetic design and code optimization of software. especially, all of the following arithmetics or conceptions are worked out in the research of software design : self - adaptable compression arithmetic based on dictionary model for data collection system, similarity full binary sort tree, a optimized quick search arithmetic and an improved arithmetic of multiplication in the floating - point operation. and all of the arithmetic are designed with mcs - 51 assembly language. the quick search arithmetic, in which merits of both binary search and sequence search are used fully, are based on the specialty of preorder traversal in similarity full binary sort tree

    特別在軟體設計研究中，提出了適用於數據採集系統的數據壓縮演算法? ?基於字典模型的自適應壓縮演算法；提出了類滿二叉排序樹的定義；提出了基於類滿二叉排序樹的先序遍歷特性的最優化快速查找演算法，它充分利用了折半查找和順序查找各自的優點；提出了浮點運算乘法的改進演算法；並在mcs - 51匯編語言層次上對所有的演算法加以實現。
  4. At first, based on the simple genetic algorithm, an improved ga which adopts a combination of emigration policy and adaptive operator is presented. results of numerical optimization show that the improved ga is effective on preventing premature problem

    本文在基本遺傳演算法的基礎上首先研究了浮點編碼遺傳演算法在數值優化中的應用，通過引進「移民策略」和自適應運算元相結合的方法，改進了基本遺傳演算法在後期進化緩慢的問題，極大地減少了早熟性收斂的現象。
  5. According to characteristics of the seismic data from the low snr region with complex surface, this paper is started from solving the static correction problem and reasonable eliminating all kinds of disturbance in the seismic data from the low snr region with complex surface. through the whole process of seismic data processing which includes a series of processing methods that are suitable for the low snr region, namely, from the choosing of the floating base - level, the static correction in the field and indoors, the eliminating of all kinds of noise before and after stacking, the velocity analysis with high - resolution, the reasonable techniques of deconvolution before stacking and wavelet processing after stacking, to the method choosing of the high - resolution stacking and the reasonable and accurate offset imaging, a set of the complete and effective flow for processing seismic data from the low snr region with complex surface are finally formed, which can meet the need of explo

    本文針對復雜地表低信噪比地區地震資料的特點，以解決復雜地表低信噪比地區地震資料靜校正問題及合理剔除各類干擾為出發點，在整個地震資料處理過程中，從浮動基準面的選取、野外及室內靜校正、疊前疊后各類噪音的去除、高精度速度分析、合理的疊前反褶積及疊后子波處理技術、到選用高精度的疊加技術及合理準確的偏移成像方法等一系列適合於復雜地表低信噪比地區的處理方法，最終形成一套較完整且有效的針對復雜地表低信噪比地區地震資料的處理流程。
  6. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  7. Radix - independent floating - point arithmetic

    與基數無關的浮點運算
  8. Floating - point arithmetic overflow or division by zero never throws an exception, because floating - point types are based on ieee 754 and so have provisions for representing infinity and nan not a number

    浮點算術溢出或被零除從不引發異常，因為浮點類型基於ieee 754 ，因此可以表示無窮和nan （不是數字） 。
  9. A integrated algorithm of ambiguity resolution is proposed. by using triple carrier phase, integer gauss transformations, qr factorization, cholesky factorization, and geometry constraint, the correlation between ambiguity components is reduced, and more error ambiguity can be discarded, also process of ambiguity searching getting rapidly. the ratio test combining constraint of baseline is used to fix ambiguity rapidly

    利用三差最小二乘求解模糊度浮點解，然後採用整數高斯變換降低模糊度分量間的相關性，再根據qr分解和基線幾何約束減少需搜索的模糊度組合，採用cholesky分解在搜索過程中及早淘汰不正確的模糊度組合，最後利用ratio檢驗與基線幾何約束條件相結合檢驗模糊度組合，盡快固定正確的模糊度。
  10. A novel algorithm for decomposing any signal into a linear expansion of elementary functions with a redundant dictionary is proposed

    摘要在分析總結浮點數編碼和格雷碼編碼各自特點的基礎上，提出了一種用浮點數和格雷碼混合編碼的遺傳演算法來實現匹配追蹤演算法。
  11. In the constructing of the diagnosis module using the technology of the combination of the fuzzy logic and neural network, which based on the fuzzy adaptive learning control network, a simple kind of capable method for consummate the structure and performance of network is introduced, which includes the rules extraction based on the maximum weights matrix and the parameters amendment based on genetic algorithm by floating - point coding. during the monitoring of the parts condition, the output of the condition monitoring system shows the good working condition of the executing agency by fuzzily deducing from the control instruction send by the auv ' s controller and motion status, and so offers the proof to complete mission and return safely

    在珍斷模塊建模中採用模糊邏輯與神經網路結合的技術，以模糊自適應學習控制網路為核心，提出了一種簡單可行的基於最大權值矩陣的規則提取及基於浮點數編碼的遺傳演算法的參數調整的，完善網路結構與性能的方法，並在狀態監測過程中，通過對由控制器輸入的水下機器人運動控制量以及運行狀態的模糊推理，得到執行部件（推進器或舵）的工作狀態優劣程度，為保證水下機器人完成任務，安全返回提供控制依據。
  12. 4. to the situations of short - baseline, a genetic algorithm of search for ambiguity solution with horizontal model is studied

    針對短基線的情況，研究基於平面模型的浮點數遺傳搜索演算法來確定整周模糊度。
  13. Different with traditional microprocessor which solves floating - point normalization with soft ware, the project implemented floating - point normalization with hard ware. the research focused on the architecture of microprocessor mainly

    因本課題意在實現微處理器的基本結構，並未涉及到編譯器，因此在對微處理器的浮點處理單元的規格化演算法進行深入分析的基礎上提出了用硬體實現浮點單元規格化的方法。
  14. 1 schmookler m s, nowka k j. leading zero anticipation and detection - a comparison of methods. in proc. 15th ieee symposium on computer arithmetic, vail, co, usa, june 11 - 13, 2001, pp. 7 - 12

    該前導0預測糾正演算法對于尾數和為正數或者負數的情況下都能正確工作，因此不需要事先判斷尾數大小和進行尾數交換，適合在基於雙通路結構的高性能浮點加減運算中採用。
  15. The proposed approach enables parallel execution of conventional lza and its error detection, so that the error - indication signal can be generated earlier in the stage of normalization, thus reducing the critical path and improving overall performance. the circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work

    本文提出了一種新型的基於錯誤糾正機制的前導0預測演算法，該演算法在傳統非精確演算法的基礎上增加了對其結果出錯時的預判機制和規格化過程中的實時糾正機制，從而實現了尾數和規格化時的精確移位，降低了浮點加減運算的關鍵路徑延遲。
  16. The primary contents and innovations of this article are introduced below. in order to take advantage of the high speed of calculation, and at the same time, improve the accuracy and dynamic - range of the algorithm, three kinds of multi - input floating point adder algorithm ( fpa ) are summarized and a high - performance multi - input fpa structure is put forward with a self - defined floating point format. the performance of the high - performance structure on calculation speed and logic resource consuming is better than the normal structure

    論文的主要工作及創新點如下:為了充分利用fpga處理速度快的特點，同時盡量提高演算法的精度及動態范圍，本文在對浮點加法器演算法進行深入研究的基礎上，規納總結了三種不同的多輸入浮點加法器演算法，並創造性地提出了一種高效的多輸入浮點加法器結構及一種適合於fpga實現的自定義浮點數格式，這種高效的結構在所需的邏輯資源和運算速度上均遠優于傳統的多輸入結構。
  17. This method is especially simple and easy to implement. furthermore, it fully capable of tracking digital control signals carried by 4 ~ 20ma analog signals ; during software development phase, we have completed signal collecting, lcd displaying, d / a converting of hart signal and ieee - 754 32 bit float point conversion. we used a simplified method in ieee - 754 32 bit compatible float point conversion based on the 24 bit integer and 16 bit decimal computation

    在hart信號的解調外圍電路中採用遲滯比較電路實現波形的轉化，這種方法簡單、易實現，完全能夠跟蹤加載在4 20ma模擬信號上的數字控制信號；在軟體設計中，完成了hart信號的採集編程、 lcd顯示編程、 d a轉化控制編程和ieee - 75432位浮點數的轉化編程， ieee - 75432位浮點數轉化編程採用的是在最多滿足24位整數位和16位小數位的基礎上的一種簡化演算法。
  18. At first, we introduce the working flow of ir image processing and the structure of the image processor, then we present the goal of the design : image pre - processing and data communication. in the part of the image pre - processing, the factors causing the nonuniformity of fpas are analyzed particularly, and several. resolutions are presented, which characters are illustrated at last. according to the design requirement, we decided to implement the two - point nonuniformity correction method in fpga

    在圖像預處理部分，首先就紅外成像傳感器非均勻性的成因進行了詳細分析，總結了紅外成像傳感器非均勻性校正的主要方法，分析了各種方法的優缺點；根據成像制導信息處理機實時處理的要求，利用現場可編程門陣列實現了基於浮點運算的兩點法非均勻性校正模塊。
  19. A large array of products are built around highly modified powerpc 400 family cores, not the least of which is the blue gene supercomputer with two powerpc 440 processors and two fp floating point cores per chip

    大量的產品都是在對powerpc 400系列的核心進行高度修改而構建的，其中「藍色基因」超級計算機就在每個晶元中採用了兩個powerpc 440處理器和兩個fp （浮點）核心。
  20. This dissertation develops research work for some fields in which ground clutter suppression algorithm may be used for airborne phased - array radar, software design of 3dt - - stap algorithm with adaptive space - frequence steer vector algorithm is completed for clutter suppression realtime processing system based on tigersharc ts101 chip

    本論文圍繞機載相控陣雷達的空時二維處理技術展開研究工作，主要任務是為系統選擇地雜波抑制的演算法，並完成以浮點dsp晶元（ ts101 ）為核心的基於3dt
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