浮點處理單元 的英文怎麼說
中文拼音 [fúdiǎnchǔlǐdānyuán]
浮點處理單元
英文
floating process unit- 浮 : Ⅰ動詞1 (漂在液體表面) float; drift 2 [方言] (在水裡游) swim Ⅱ形容詞1 (在表面上的) superfici...
- 點 : Ⅰ名詞1 (液體的小滴) drop (of liquid) 2 (細小的痕跡) spot; dot; speck 3 (漢字的筆畫「、」)...
- 處 : 處名詞1 (地方) place 2 (方面; 某一點) part; point 3 (機關或機關里一個部門) department; offi...
- 理 : Ⅰ名詞1 (物質組織的條紋) texture; grain (in wood skin etc ) 2 (道理;事理) reason; logic; tru...
- 浮點 : [計算機] floating decimal; floating point
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Fpu : floating - point processing unit
浮點處理單元There are five parts in powerpc603e ? microprocessor : integer execution unit, floating point unit ( fpu ), instruction ( data ) cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way
Powerpc603e微處理器系統由定點執行單元、浮點單元、指令(數據) cache 、總線介面單元、存儲管理單元組成,以流水和超標量方式執行指令。It has five parts, such as integer execution unit, floating point unit ( fpu ), instruction cache, bus interface unit and memory manage unit. the instructions are executed with pipeline way. the instruction set and i / o signals are compatible with powerpc
它由定點執行單元、浮點單元、指令cache 、總線介面單元、存儲管理單元組成,以流水和超標量方式執行指令,指令集和介面時序兼容powerpc ,是典型的risc微處理器結構。After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper
此外,本文還對處理器的浮點運算單元設計做了初步的研究,以ansi ieee - 754浮點數二進制標準為參考,借鑒了經典的定點加法器和乘法器的設計,嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述,並對其進行模擬和驗證。Different with traditional microprocessor which solves floating - point normalization with soft ware, the project implemented floating - point normalization with hard ware. the research focused on the architecture of microprocessor mainly
因本課題意在實現微處理器的基本結構,並未涉及到編譯器,因此在對微處理器的浮點處理單元的規格化演算法進行深入分析的基礎上提出了用硬體實現浮點單元規格化的方法。Amex86 microprocessor is composed of integer processing unit, float - point processor unit ( math coprocessor ) and protect test unit
Amex86系統由一個整數處理部件( cpu ) 、一個浮點處理部件(數學協處理器)和一個保護測試單元組成。Floating - point unit is a special microprocessor circuitry unit that deals with floating - point arithmetic operations, which is widely used in scientific arithmetic, cpu, dsp ( digital signal processing ) and image processing, the thesis discusses how to implement high - performance floating - point processing unit based on the research of its implementation algorithm and its implementation structure
浮點運算單元( fpu )是處理器中專門進行浮點算術運算的電路單元,廣泛應用在科學計算、 cpu 、 dsp和圖象處理。論文從浮點運算單元的實現演算法和結構的研究出發,討論如何實現高性能浮點運算單元。Based on s698 technology, obt - devsys - s698 is one of the serial s698 - mil application development systems including 32 - bit embedded processor with 32 64 - bit fpu 160mhz processing speed sram memory controller flash memory controller uart ps 2 led interrupter controller, etc. the bus interfaces is composed of i2c spi magnetic card interface and ic card interface. obt - devsys - s698 carries on the advantages of s698 serial module such as compact structure and reasonable composition
Obt - devsys - s698是s698系列嵌入式處理器開發板中的一員,其上包括:具有32 64 - bit浮點運算單元的32 - bit嵌入式處理器,主頻160mhz , sram存儲器, flash存儲器具有三路uart介面,一路ps 2介面, led發光二極體控制電路,中斷操作按鈕其外擴總線包括i2c總線介面spi總線介面磁卡介面智能卡介面等。The research work of this thesis mainly includes : research of floating point algorithm, including addition, subtraction, multiplication, division, evolution and cordic ( coordinate rotation digital computer )
?對powerpc603e浮點處理單元( fpu )中採取演算法的進行選擇和驗證,主要包括:改進的booth演算法和goldschmidt演算法。Optimized 32 64 - bit floating - point unit, conforming to ieee - 754 standard
位浮點處理單元,遵循The power2 added a second floating - point unit and more cache
Power2晶元中新加了第二個浮點處理單元( fpu )和更多緩存。In the project, the microprocessor is composed of integer unit and floating - point unit
本課題所設計的微處理器共包括兩部分:整數單元和浮點單元。To decrease the area of the chip, resource sharing, which is a synthesized optimized method of eda tools, was used in the project. the code was verified in fpga soft ware environment. synthesized netlists based on fpga and asic were given in the paper for future work
本課題所設計的微處理器的整數單元和浮點單元均採用硬體描述語言vhdl進行建模,為降低晶元面積,將資源共享這一eda工具的綜合優化方法應用於設計中,並在現有條件下進行了簡單的fpga驗證,考慮到今後的asic設計,本文給出了基於fpga和基於asic的兩種綜合網表。分享友人