浮點計數器 的英文怎麼說

中文拼音 [fúdiǎnjìshǔqì]
浮點計數器 英文
floating number
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 浮點 : [計算機] floating decimal; floating point
  • 計數 : count; tally; counting計數卡 numbered card
  1. In digital relay, the percentage of noise will increase rapidly with the increase of sampling rate when derivation calculus is substituted by sampled difference term. to solve this problem, a new method using fragment function integrated with the least square algorithm is proposed in this paper. the influence of white noise is greatly reduced and the accuracy of the dead angle calculation is nicely improved after adopting the new method

    在數字式保護中，如果用差分代替求導將導致噪聲的百分比誤差隨著采樣頻率的提高而劇增，本文對此進行了分析並提出了用分段樣條函數最小二乘法來計算電流波形的導數值，以便在提高采樣率的同時降低噪聲誤差的影響，並將其應用於基於32位浮點dsp的新型變壓器保護裝置。
  2. Design of a parameterized floating point multiplier

    一種浮點乘法器的參數化設計
  3. A data acquisition system with the following features is realized : ? transmission rate up to 100kbyte / s over usb ; ? system ' s dynamic range as high as 120 db ; ? multi - kind of trigger mode control ; ? sampling rate as high as 100 ksps ; ? 12 - bit a / d conversion accuracy ; ? 32k bytes on - board data memory ; ? the system, which was made up of large - scale electronic chips, is small, light and portable, and suitable for field use

    本設計最終實現了一個瞬態信號數據採集系統，它具有以下特點： ?採用usb介面進行高速數據傳輸，傳輸速度達100kbyte / s ； ?採用浮點a / d轉換技術，動態范圍達120db ； ?多種采樣觸發控制方式； ?最高采樣率100ksps ； ? 12位采樣精度： ? 32kb數據緩存； ?使用新型大規模電子器件，系統結構緊湊，重量輕，適合野外作業。
  4. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  5. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  6. This article deals with the method to determine the guard digit in the left normatlization of float point number in the analysis and design of computer system, and briefly introduces its application in practice

    摘要介紹了在計算機系統分析和設計中，用於浮點數左規格化的警戒位的設置方法，並簡要說明了該類警戒位與用於舍入的警戒位共同組成了運算器中的累加器的實際警戒位字長。
  7. This is a mathematical calculator designed for single - hand operation, a key figure refers to each wide support floating - point operations. press vivid and lively design

    這是一個為單手操作設計的數學計算器，每個數字鍵有一指寬支持浮點運算，按鍵設計活潑生動
  8. Become a kind of new electronics circuit - current - mode circuit. it is replacing the traditional design method of the voltage - mode in the high frequency high - speed signal processing realm 。 this thesis mainly discussed the modified second - generation current conveyors based on the current - mode kinds of new cuicuit components, they are stronger modified standard current - mode parts in fuctions on this foundation. mainly including the modified differential difference current conveyor ( mddccii ) 、 the fully balanced second generation current conveyor ( fbccii ) 、 ( full balances ) four - terminal floating nullor ( fbftfn ) and the current differencing buffered amplifier ( cdba ), they are all function very strong standard current - mode parts, they all can provide some circuit functions of better than general operation amplifier, because they have the voltage importation and the current importation, therefore use it since can carry out the voltage - mode signal processing circuit expediently, can also carry out the current - mode signal processing circuit expediently, and have to increase the benefit bandwidth to accumulate more widely than the voltage - mode, but have their advantages more according to the current - mode filter of the modified current conveyor, because it constitutes in brief, the filter wave function is stronger and they are better than in general use operation amplifier of many advantages, be easy to composing for example 、 high speed 、 frequency bandwidth 、 the power supply voltage requests low 、 consume small, the impedance is different from etc. advantages, otherwise they have biggish dynamic range, and flexible circuit synthesize, so they are the best active parts

    從第二代電流傳輸器ccii入手，重點研究了以下幾種改進型的第二代電流傳輸器:改進的差動差分電流傳輸器mddccii 、全平衡第二代電流傳輸器fbccii 、多輸出四端浮地零器ftfn 、全平衡四端浮地零器fbftfn 、電流差分緩沖放大器cdba的電路結構及其模型。然後在此基礎上系統地研究了基於這幾種改進型的第二代電流傳輸器的濾波器的設計方法，主要方法和結果如下:利用mddccii設計了差分式連續時間電流模式低通、帶通濾波器;電流模式跳耦結構考爾低通濾波器;利用fbccii設計了帶通二階節濾波器及電流模式雙二階通用濾波器;設計了基於多輸出端ftfn的電流模式二階通用濾波器電路;通過數字化開關選擇的基於fbftfn的電流模式通用濾波器;設計了基於最少個數電流緩沖放大器（兩個cdba ）的多功能通用電流模式濾波器及其在非理想因素情況下分析。設計濾波器的主要方法是採用級聯設計、運算模擬（信號流圖法）和反饋設計（跳耦法） 。
  9. Finally, the principle of phase - locked - loop for speed control is discussed. the control methods of torque and magnetic levitation force are studied experimentally on a prototype bearingless motor. based on the analysis of shortcomings of the analog control system, a digital control system is proposed

    分析了採用鎖相環對電機轉速進行閉環控制的原理；設計了磁懸浮力的模擬控制器並對磁懸浮血泵電機進行了實驗研究；針對模擬控制系統存在的缺點，本文設計了一種數字控制系統。
  10. In this paper, the dynamic characteristics associated with the high - speed maglev vehicle and guideway coupling system has been studied. two issues are discussed : one is the asymptotic stability of the system and the other is the coupling vibration characteristic. the basic relation between the control, structure and coupling parameters is studied emphatically to trace the rule of the vibration and to give help for the design of guideway, vehicle structures and controller

    本文選擇高速磁浮列車系統懸浮方向的車軌耦合動力學特性作為研究對象，分析車軌耦合動力學的兩個基本問題:系統漸近穩定性和車軌耦合振動特性，重點研究控制、結構和各種耦合參數與這兩項系統特性的關系，目的在於尋找車軌耦合振動的規律，為軌道、車輛結構和控制器設計提供參考。
  11. The characteristics for this type of heat exchanger are various standards, different shapes, multi - usefulness, completed specifications and same structure but large changing range of sizes for same series. by means of developing the database and drawing libraries, parameterized designing of pipe group units, the cad system for floating - end heat exchanger was developed base on the theory of fixed patterns with flexible sizes

    本文針對浮頭式換熱器規格品種繁多、形式各異、使用廣泛、產品設計標準完善、同系列產品圖形結構相同、尺寸變化跨度大的特點，通過數據庫和圖庫的開發、管束組件的參數化設計，運用「死圖活尺寸」的開發理念，研究和開發了浮頭式換熱器輔助設計系統。
  12. The floating - point a / d conversion scheme was employed to increase the system ' s dynamic range. complex programmable logic device ( cpld ) was also used to perform the system ' s function such as data sampling trigger control and data storage control, etc. aduc812, a new type of microprocessor with full a / d converter, was utilized to fulfill the a / d conversion

    在數據採集電路設計中，採用了浮點放大技術來提高系統的動態范圍；通過引入可編程邏輯器件來實現觸發控制、存儲控制；采樣過程中應用了時序重疊技術，從而實現了數據採集系統的流水線作業方式。
  13. Due to high speed of the maglev, it demands rapidity and reliability of the communication interface between gap sensor and suspense control system. thus a multi - serial asynchronous communication interface based on rs - 485 is designed. it transmits one signal on each unattached channel and has redundant structure, which meets the requirement of rapidity and reliability

    針對磁懸浮列車，對間隙傳感器與懸浮控制器之間通訊介面的實時性和可靠性高要求特點，本文還設計了多路rs - 485串列異步通訊介面，每路通道傳送一路數據，各路通道之間相互冗餘，滿足了系統對實時性與可靠性方面的要求。
  14. In the project, the microprocessor is composed of integer unit and floating - point unit

    本課題所設計的微處理器共包括兩部分：整數單元和浮點單元。
  15. To decrease the area of the chip, resource sharing, which is a synthesized optimized method of eda tools, was used in the project. the code was verified in fpga soft ware environment. synthesized netlists based on fpga and asic were given in the paper for future work

    本課題所設計的微處理器的整數單元和浮點單元均採用硬體描述語言vhdl進行建模，為降低晶元面積，將資源共享這一eda工具的綜合優化方法應用於設計中，並在現有條件下進行了簡單的fpga驗證，考慮到今後的asic設計，本文給出了基於fpga和基於asic的兩種綜合網表。
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