浮點計數法 的英文怎麼說

中文拼音 [fúdiǎnjìshǔfǎ]
浮點計數法 英文
floating point notation
  • 浮 : Ⅰ動詞1 （漂在液體表面） float; drift 2 [方言] （在水裡游） swim Ⅱ形容詞1 （在表面上的） superfici...
  • 點 : Ⅰ名詞1 （液體的小滴） drop （of liquid） 2 （細小的痕跡） spot; dot; speck 3 （漢字的筆畫「、」）...
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 數 : 數副詞（屢次） frequently; repeatedly
  • 法 : Ⅰ名詞1 （由國家制定或認可的行為規則的總稱） law 2 （方法; 方式） way; method; mode; means 3 （標...
  • 浮點 : [計算機] floating decimal; floating point
  • 計數 : count; tally; counting計數卡 numbered card
  1. In digital relay, the percentage of noise will increase rapidly with the increase of sampling rate when derivation calculus is substituted by sampled difference term. to solve this problem, a new method using fragment function integrated with the least square algorithm is proposed in this paper. the influence of white noise is greatly reduced and the accuracy of the dead angle calculation is nicely improved after adopting the new method

    在數字式保護中，如果用差分代替求導將導致噪聲的百分比誤差隨著采樣頻率的提高而劇增，本文對此進行了分析並提出了用分段樣條函數最小二乘法來計算電流波形的導數值，以便在提高采樣率的同時降低噪聲誤差的影響，並將其應用於基於32位浮點dsp的新型變壓器保護裝置。
  2. Vol. 121 of the ima volumes in mathematics and its applications, springer - verlag, berlin heidelberg, 2000, pp. 59 - 82. 9 murray j d. mathematical biology ii : spatial models and biomedical applications. 3rd edition, springer verlag, january 2003, pp. 141 - 191

    這樣，在存儲四個浮點數后，旋轉計算時，只需要12次加法和12次乘法將四元組轉為矩陣，並對一個頂點只進行6次加法和9次乘法。
  3. Design of a parameterized floating point multiplier

    一種浮點乘法器的參數化設計
  4. The approximate computation method is used in float point computation of system ' s control algorithms on fixed - point dsp after comparing several methods in respect of running time and program space involved, which attains quick computation besides high precision and implements output voltaic with low harmonic and high control precision of frequency

    通過從運行時間和佔用空間等方面比較在定點dsp上實現浮點數運算的幾種方法，並選擇了近似計演算法作為系統控制演算法浮點數運算的方法，在保證足夠計算精度的前提下達到計算的快速性，實現低諧波和頻率控制精度高的輸出電壓。
  5. In this paper, a lot of researches and exploration are applied to studying the universality and expansibility of hardware and the arithmetic design and code optimization of software. especially, all of the following arithmetics or conceptions are worked out in the research of software design : self - adaptable compression arithmetic based on dictionary model for data collection system, similarity full binary sort tree, a optimized quick search arithmetic and an improved arithmetic of multiplication in the floating - point operation. and all of the arithmetic are designed with mcs - 51 assembly language. the quick search arithmetic, in which merits of both binary search and sequence search are used fully, are based on the specialty of preorder traversal in similarity full binary sort tree

    特別在軟體設計研究中，提出了適用於數據採集系統的數據壓縮演算法? ?基於字典模型的自適應壓縮演算法；提出了類滿二叉排序樹的定義；提出了基於類滿二叉排序樹的先序遍歷特性的最優化快速查找演算法，它充分利用了折半查找和順序查找各自的優點；提出了浮點運算乘法的改進演算法；並在mcs - 51匯編語言層次上對所有的演算法加以實現。
  6. In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future

    第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpga
  7. The algorithm and its implementation of the leading zero anticipation are very vital for the performance of a high - speed floating - point adder in today s state of art microprocessor design. unfortunately, in predicting " shift amount " by a conventional lza design, the result could be off by one position. this paper presents a novel parallel error detection algorithm for a general - case lza

    目前國際上已有很多演算法對前導0預測演算法進行了研究，但是出於設計方法和延遲等方面的限制，大部分前導0預測演算法都為非精確演算法，其預測結果可能與真實加法結果中前導0的個數產生一位的誤差，這個誤差需要在浮點加法的后規格化過程中進行修正，因此反過來又增加了浮點加減演算法的關鍵路徑延遲。
  8. After that, it gives the measures of designing dsp ' s assembler as a part of the dsp ' s software development environment together with the c - compiler. moreover, this paper explores the method of design the floating - point arithmetic unit. referring to the ieee754 - 1985 standard for binary floating - point arithmetic, the algorithm and the behavior description of floating - point adder and multiplier is given, and the simulation and verification is shown at the end of this paper

    此外，本文還對處理器的浮點運算單元設計做了初步的研究，以ansi ieee - 754浮點數二進制標準為參考，借鑒了經典的定點加法器和乘法器的設計，嘗試性的給出了浮點加法單元和乘法單元的實現模型和行為級上的硬體描述，並對其進行模擬和驗證。
  9. This article deals with the method to determine the guard digit in the left normatlization of float point number in the analysis and design of computer system, and briefly introduces its application in practice

    摘要介紹了在計算機系統分析和設計中，用於浮點數左規格化的警戒位的設置方法，並簡要說明了該類警戒位與用於舍入的警戒位共同組成了運算器中的累加器的實際警戒位字長。
  10. Become a kind of new electronics circuit - current - mode circuit. it is replacing the traditional design method of the voltage - mode in the high frequency high - speed signal processing realm 。 this thesis mainly discussed the modified second - generation current conveyors based on the current - mode kinds of new cuicuit components, they are stronger modified standard current - mode parts in fuctions on this foundation. mainly including the modified differential difference current conveyor ( mddccii ) 、 the fully balanced second generation current conveyor ( fbccii ) 、 ( full balances ) four - terminal floating nullor ( fbftfn ) and the current differencing buffered amplifier ( cdba ), they are all function very strong standard current - mode parts, they all can provide some circuit functions of better than general operation amplifier, because they have the voltage importation and the current importation, therefore use it since can carry out the voltage - mode signal processing circuit expediently, can also carry out the current - mode signal processing circuit expediently, and have to increase the benefit bandwidth to accumulate more widely than the voltage - mode, but have their advantages more according to the current - mode filter of the modified current conveyor, because it constitutes in brief, the filter wave function is stronger and they are better than in general use operation amplifier of many advantages, be easy to composing for example 、 high speed 、 frequency bandwidth 、 the power supply voltage requests low 、 consume small, the impedance is different from etc. advantages, otherwise they have biggish dynamic range, and flexible circuit synthesize, so they are the best active parts

    從第二代電流傳輸器ccii入手，重點研究了以下幾種改進型的第二代電流傳輸器:改進的差動差分電流傳輸器mddccii 、全平衡第二代電流傳輸器fbccii 、多輸出四端浮地零器ftfn 、全平衡四端浮地零器fbftfn 、電流差分緩沖放大器cdba的電路結構及其模型。然後在此基礎上系統地研究了基於這幾種改進型的第二代電流傳輸器的濾波器的設計方法，主要方法和結果如下:利用mddccii設計了差分式連續時間電流模式低通、帶通濾波器;電流模式跳耦結構考爾低通濾波器;利用fbccii設計了帶通二階節濾波器及電流模式雙二階通用濾波器;設計了基於多輸出端ftfn的電流模式二階通用濾波器電路;通過數字化開關選擇的基於fbftfn的電流模式通用濾波器;設計了基於最少個數電流緩沖放大器（兩個cdba ）的多功能通用電流模式濾波器及其在非理想因素情況下分析。設計濾波器的主要方法是採用級聯設計、運算模擬（信號流圖法）和反饋設計（跳耦法） 。
  11. The approximate computation method is used in float point computation of system ' s control algorithms after comparing several methods in respect of running time and program space involved, which attains quick computation besides high precision and implements excitation voltage with low harmonic and high control precision of frequency

    通過從運行時間和佔用空間等方面比較實現浮點數運算的幾種方法，並選擇了近似計演算法作為系統控制演算法浮點數運算的方法，在保證足夠計算精度的前提下達到計算的快速性，實現低諧波和頻率控制精度高的勵磁電壓。
  12. On the one hand it is important for the design of floating - point processor unit to optimize speed while algorithms of high - speed are introduced. for examples, two - path of high - speed floating - point addition, booth coding of floating - point multiplication. srt of floating - point division and square root, cordic of transcendental function and so on

    一方面浮點處理部件設計重點在於速度的優化，所以採用優化的高速演算法，如浮點加法的two - path 、浮點乘法的booth編碼、浮點除法和平方根的srt演算法以及超越函數的cordic演算法等。
  13. In chapter one the types and characteristic of ultraphytoplankton are introduced first, then the working principle and protocols of flow cytometry for ultraphytoplankton measurements are also presented. the main purpose of this part is to make good understanding of the works in east china sea and yellow sea

    在第一章中重點介紹了超微型浮游植物的主要類型、特點，和流式細胞計檢測超微型浮游植物的原理與方法，本文所採用的主要研究方法如采樣、測試及數據分析等均在這一章中給出，以便對在東、黃海的工作結果有清楚的理解。
  14. Signed floating point or signed scientific notation, whichever is shorter

    Signed浮點型或signed科學計數法，顯示其中較短的數
  15. The design of software adopt the method of structural programmer. it contains the following parts : water parameter module, floating - point module, data processing module, other module and subprogram. each module has its specific function

    軟體設計採用結構化程序設計的方法，分為三大模塊及輔助模塊，即：水分參數檢測模塊，浮點運算模塊、數據處現模塊、其它模塊、子程序（啟動模塊、顯示子程序、鍵掃描模塊等）每個模塊分別完成其特定的功能。
  16. This method is especially simple and easy to implement. furthermore, it fully capable of tracking digital control signals carried by 4 ~ 20ma analog signals ; during software development phase, we have completed signal collecting, lcd displaying, d / a converting of hart signal and ieee - 754 32 bit float point conversion. we used a simplified method in ieee - 754 32 bit compatible float point conversion based on the 24 bit integer and 16 bit decimal computation

    在hart信號的解調外圍電路中採用遲滯比較電路實現波形的轉化，這種方法簡單、易實現，完全能夠跟蹤加載在4 20ma模擬信號上的數字控制信號；在軟體設計中，完成了hart信號的採集編程、 lcd顯示編程、 d a轉化控制編程和ieee - 75432位浮點數的轉化編程， ieee - 75432位浮點數轉化編程採用的是在最多滿足24位整數位和16位小數位的基礎上的一種簡化演算法。
  17. Three improvements were proposed. that is : coding the chromosome with floating point numbers, selecting different optimal strategy according to the electric dimension of the target, utilizing subsection varying parameter genetic algorithm to avoid trapping in premature convergence. the optimization time was saved significantly after adopting these methods

    針對球面和半球面結構的雷達吸波材料優化設計時間長，提出三點改進方法：染色體採用浮點數編碼；依據優化目標的電尺寸採用不同的優化策略；優化過程中採用分段變參數的優化方法。
  18. The major tasks include : ( 1 ) expand the schema theorem for ga. the schema theorem with binary coding advanced by professor holland is expanded to limited integer, letter, floating point numbers the number of which value is limited, and their hybrid coding. ( 2 ) put forward replacing by the excellent chromosome ga ( recga ), superiority colony first ga ( scfga ) and improve the ga ; ( 3 ) make probability convergence analysis of recga using the theory of markov chain, random process ; ( 4 ) make convergence analysis of scfga using the principle of contractive mapping in functional analysis theory ; ( 5 ) design the test programs ( cap ) to resolve np problems ( course arrangement ) with gas ; based on recga, modify the arithmetic and then conduct tests

    主要有以下幾方面工作： （ 1 ）將二進制編碼遺傳演算法的模式定理擴展到由有限整數、字母或取值個數有限的浮點數編碼，或它們混合編碼的遺傳演算法范圍； （ 2 ）提出最佳個體替換策略遺傳演算法（ recga ） 、優勢群體優先策略遺傳演算法（ scfga ） ，對遺傳演算法進行改進； （ 3 ）使用隨機過程理論markov鏈對recga進行了收斂性分析； （ 4 ）使用泛函分析理論壓縮映射原理對scfga進行了收斂性分析； （ 5 ）使用遺傳演算法設計了解決np類問題（排課問題）的測試程序（ cap ） ，並根據recga對演算法進行改進並進行測試。
  19. In the coarse step, an improved klt ( kanade - lucas - tomasi ) algorithm is applied in feature extraction, and a new acceleratingalgorithm of template matching is presented to match features, and also a feasible feature validitytesting method is given. in the precise step, the “ regional counting method based onjoint - histogram ” is used for reference to make out its own improved method, which achieves “ sub - pixel ” precision as well as avoids heavy floating - point operation by clever definition ofcriterion function

    粗配準過程中，利用klt （ kanade - lucas - tomasi ）的改進演算法進行特徵提取，提出一種新的模板匹配加速演算法進行特徵匹配，還給出了切實可行的特徵有效性檢驗方法;精配準過程中，借鑒「聯合直方圖區域計數法」的思想，提出具體的改進方案，通過巧妙定義準則函數使得演算法在避開大量浮點運算的同時達到了亞像素級精度。
  20. To decrease the area of the chip, resource sharing, which is a synthesized optimized method of eda tools, was used in the project. the code was verified in fpga soft ware environment. synthesized netlists based on fpga and asic were given in the paper for future work

    本課題所設計的微處理器的整數單元和浮點單元均採用硬體描述語言vhdl進行建模，為降低晶元面積，將資源共享這一eda工具的綜合優化方法應用於設計中，並在現有條件下進行了簡單的fpga驗證，考慮到今後的asic設計，本文給出了基於fpga和基於asic的兩種綜合網表。
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