深亞微米 的英文怎麼說
中文拼音 [shēnyǎwéimǐ]
深亞微米
英文
deesubmicronn-
This thesis mainly addresses the design of 8 - bit cisc soft ip - 08c01, based on dsm technology
本論文的主要工作是以8位微處理器軟ip ? 08c01為載體，對基於深亞微米工藝的ip設計技術進行研究。Numerical simulation of air sliders in an ultra sub - micron flying system
深亞微米飛行系統滑塊的數值模擬Developing the lithography process models to properly characterize critical dimension ( cd ) variations caused by proximity effects and distortions introduced by patterning tool, reticule, resist exposure, development and etching, they are beneficial to develop a yield - driven layout design tool, the engineers could use it to automate the tasks of advanced mask design, verification and inspection in deep sub - micron semiconductor manufacturing
建立準確描述由於掩模製造工藝、光刻膠曝光、顯影、蝕刻所引起的光學鄰近效應和畸變所導致的關鍵尺寸變化的光刻工藝模型，有助於開發由成品率驅動的版圖設計工具，自動地實現深亞微米下半導體製造中先進的掩模設計、驗證和檢查等任務。This paper summarizes the present situation of modern microelectronic device is. with integrated degree of circuits increasing, and the characteristic sizes of technics minishing as well as the device sizes turning into sub - micron and deep sub - micron, there are many problems
概述了現代微電子器件發展的現狀，電路集成度的不斷提高，加工工藝特徵尺寸的不斷減小，器件尺寸進入了亞微米、深亞微米階段，出現了許多不良效應。Interconnect wire delay questions in deep submicron ic design
深亞微米集成電路設計中的互連線延遲問題Adopts vdsm process technology however two outstanding problems are faced to ic layout design when the feature size reaches to 0. 18 m or lower : 1. timing convergence problem seriously affects the circuits schedule, and the interconnect - delay has exceeded more than 70 % of the total circuits ’ delay. 2. si problem, usually it consists two aspects of ir - drop and crosstalk. these problems often affect the chip function after tapout
本篇論文就是針對超深亞微米階段soc晶元後端設計所面臨的挑戰，提出了運用連續收斂的布局布線策略，尤其是虛擬原型的設計理論，來快速驗證布局，進而提高布線的成功率，並且提出了一種改進的布局評估模型，提高對soc晶元預測布線的準確度;同時，對于時鐘驅動元件選擇，文中提出了一種基於正態分佈模型來達到更有效的選取。Based on the hydrodynamic energy transport model, the influence of variation of negative junction depth caused by concave depth on the characteristics of deep - sub - micron pmosfet has been studied. the results are explained by the interior physical mechanism and compared with that caused by the source / drain depth. research results indicate that with the increase of negative junction depth ( due to the increase of groove depth ), the threshold voltage increases, the sub - threshold characteristics and the drain current driving capability degrade, and the hot carrier immunity becomes better in deep - sub - micron pmosfet. the short - channel - effect suppression and hot - carrier - effect immunity are better, while the degradation of drain current driving ability is smaller than those with the increase of depth of negative junction caused by source / drain junction shallow. so the variation of concave depth is of great advantage to improve the characteristics of grooved - gate mosfet
基於能量輸運模型對由凹槽深度改變引起的負結深的變化對深亞微米槽柵pmosfet性能的影響進行了分析，對所得結果從器件內部物理機制上進行了討論，最後與由漏源結深變化導致的負結深的改變對器件特性的影響進行了對比.研究結果表明隨著負結深（凹槽深度）的增大，槽柵器件的閾值電壓升高，亞閾斜率退化，漏極驅動能力減弱，器件短溝道效應的抑制更為有效，抗熱載流子性能的提高較大，且器件的漏極驅動能力的退化要比改變結深小.因此，改變槽深加大負結深更有利於器件性能的提高Experimental results in this paper show our approaches can be efficiently used in delay testing for complex circuits with noise effects
實驗表明，本文的方法可以應用在復雜超深亞微米電路的延時故障測試中，有一定推廣價值。With turning the scale of asic ( appl ication specified integrated circuits ) to s0c ( system on chip ), which conunon1y is composed of mcu, specified function ip cores, memory, periphery interface etc, the ip reuse techno1ogy is very important in s0c design flow, which can realize the constructions of different levels components. the approach of configurable system, method and design f1ow for udsm ( u1tra deep sub micron ) asic, logic system design using hdl 1anguage, coding style, static and dynamic verification strategy are a1so presented in chapter 2. in chapter 3 we study the vlsi - - dsp architecture design, dense computation and high speed high performance digital signal processing unit structure, which includes high speed mac components and distributed arithmetic unit
在工程設計方法及結構化設計和高層次綜合的研究中，介紹了在深亞微米工藝條件使用的方法和asic設計流程，討論了高層次綜合的核心如何從描述推出電路構成的設計思路，針對不同目標的設計技巧討論了採用hdl語言進行邏輯系統設計的方法，給出了用vhdl語言進行代碼設計時的規范和風格，在面向soc的驗證策略討論了動態和靜態的驗證技術，提出了進行單獨模塊驗證、晶元的全功能驗證和系統軟硬體協同驗證的整體策略。Also from waveform polynomials of sequential circuits, a precise clocking method based on multiple - period sensitization is presented. a novel noise estimation method based on boolean process is first presented in this paper, using transition numbers to describe noise effects. then combined with the selection method of long sensitization paths based on waveform sensitization, a test generation approach that could generate the noisiest sensitization waveforms for long sensitizatizable paths is presented
為了適應超深亞微米電路測試的要求，本文建立了一種新的基於布爾過哈爾濱工程大學博士學位論文程論的邏輯級噪聲預測模型，用波形多項式描述的同時發生的跳變數來預測l卜足聲大小，並生成能產生最大跳變數目的輸入波形;然後同基於波形敏化的長敏化通路選擇法相結合，形成一種能產生最大噪聲效應的敏化測試波形生成新方法。In iddq detecting area, the basic principle and strongpoint of iddq testing are introduced. then, the influence of deep - submicron technology on iddq testing is explained. and the improved iddq testing methods are also given
在靜態電流檢測方面，首先闡述了iddq檢測的基本原理以及優缺點;分析了深亞微米技術對iddq測試的影響以及iddq的改進方法。Based on the hydrodynamics energy transport model, the degradation induced by donor interface state is analyzed for deep - sub - micron grooved - gate and conventional planar pmosfet with different channel doping density. the simulation results indicate that the degradation induced by the same interface state density in grooved - gate pmosfet is larger than that in planar pmosfet, and for both devices of different structure, the impact of n type accepted interface state on device performance is far larger than that of p type. it also manifests that the degradation is different for the device with different channel doping density. the shift of drain current induced by same interface states density increases with the increase of channel do - ping density
基於流體動力學能量輸運模型，對溝道雜質濃度不同的深亞微米槽柵和平面pmosfet中施主型界面態引起的器件特性的退化進行了研究.研究結果表明同樣濃度的界面態密度在槽柵器件中引起的器件特性的漂移遠大於平面器件，且電子施主界面態密度對器件特性的影響遠大於空穴界面態.特別是溝道雜質濃度不同，界面態引起的器件特性的退化不同.溝道摻雜濃度提高，同樣的界面態密度造成的漏極特性漂移增大As the technology advances into deep sub - micron era, crosstalk reduction is of paramount importance for signal integrity. simultaneous shield insertion and net ordering sino has been shown to be effective to reduce both capacitive and inductive couplings
隨著集成電路工藝發展到深亞微米技術，互連線串擾問題變得相當重要，它與互連線時延問題成為了決定電路性能的主要因素。Longer paths tend to be sensitive to crosstalk - induced delay effects because of their short slack time
因此，超深亞微米工藝下，在設計驗證、測試階段需要對串擾問題給予認真對待。Especially with the use and advancement of vdsm ( very - deep - sub - micron ) technology, the faults during manufacturing become more multiple and difficult to test
尤其是超深亞微米（ vdsm ）工藝的使用，生產過程中出現的故障也越來越多樣、難測。With the rapid developments of slsi technology, the system on a chip ( soc ) technology supported by very deep sub - micron ( vdsm ) and ip - reuse has become the developmental trend of international slsi and the ic mainstream in the 21st century
隨著超大規模集成電路工藝技術的發展，以超深亞微米工藝和ip核復用技術為支撐的系統晶元技術（ soc ）是國際超大規模集成電路發展的趨勢和二十一世紀集成電路技術的主流。The rectilinear steiner minimal tree rsmt problem is one of the fundamental problems in physical design, especially in routing, which is known to be np - complete. this paper presents an algorithm, called aco - steiner, for rsmt construction based on ant colony optimization
製造工藝由超深亞微米vdsm進入到納米nanometer階段，作為物理設計physical design重要階段之一的布線routing ，其演算法研究與工具設計面臨新的挑戰。With the deep sub - micron process being mainstream technique in semiconductor production, the shrinking scale and the expanding size & complexity bring about a series of severe problems, which poses a great challenge on asic ( application specific integrated circuits ) design. we must consider synthesis and test requirements in the early time of front - end design
隨著超深亞微米工藝成為半導體業界的主流加工工藝，日漸細微的器件尺寸以及不斷膨脹的設計規模和復雜度引起了一系列嚴峻的問題，給asic設計帶來了巨大的挑戰，迫切要求在前端設計時就開始考慮綜合、驗證和測試的需要。When the silicon technology comes to deep sub - micron level, the interconnect delay exceeds the gate delay ; and because of the increase of 1c work frequency, the allowable errors become smaller, and the influence of the transmission delay gets bigger, which increase the difficulty of the circuit design
在深亞微米製造技術中，晶元互連線延遲超過門延遲，而且隨著集成電路工作頻率的提高，允許的時序容差變小，傳輸延遲的影響加大，設計工作難度增加。Now the technology of integrated circuit industry has already broken through the characteristic minimum size of 100nm, and the cpu based on 90nm will be launched in this year
當前集電路產業已經突破100nm工藝大關，基於90納米工藝的cpu處理器將於今年內推出，整個產業向深亞微米工藝不斷推進。分享友人