環路噪聲帶寬 的英文怎麼說
中文拼音 [huánlùzàoshēngdàikuān]
環路噪聲帶寬
英文
loonoise bandwidth-
Design a kind of sub - optimum digital prefilter. through the simulation of timing recovery loop which is n ' t added prefilter and which is added prefilter, discuss the convergence characteristic and compare the relation between timing jitter and signal to noise ratio, the relation between timing jitter and noise bandwidth of loop, the relation between symbol error ratio and signal to noise ratio
通過對加預濾波器后的定時恢復環的模擬，討論了環路的收斂情況，比較了所設計的數字預濾波器和無預濾波器時環路定時抖動與信噪比、定時抖動與環路噪聲帶寬、誤碼率與信噪比的數量關系，證實所設計的數字預濾波器對減少定時抖動非常有效。At last we introduce the realization of all the parts, the problem in the circuit design and the measured data. the results show that the designed system has met the requirement. in this dissertation, direct digital synthesis technology has been used in the phase - locked frequency synthesizer, which can make full use of the characteristics of direct digital synthesis technology such as flexible output wave shape and continuous
本課題將直接數字式合成技術用於鎖相頻率合成器中，該方法將直接數字合成的特點，如輸出波形靈活且相位連續、頻率穩定度高、輸出頻率解析度高、頻率轉換速度快、輸出相位噪聲低、集成度高、功耗低、體積小等與鎖相環路的頻帶寬、工作頻率高、頻譜質量好等優點有機的結合起來，從而在寬帶的條件下實現了比較好的雜散性能和相噪。This paper introduces the principle of phase - locked loop and analyzes the performance characteristics of pll chip adf4106 which has wide bandwidth and low power consumption. and then introduces the design method of a kind of low phase noise frequency synthesizers which uses single chip processor to control the chip. the application supplies a good design method for high frequency synthesizer
介紹了鎖相環路的工作原理，分析了低功耗寬帶集成鎖相環晶元adf4106的工作特性，並介紹了一種利用單片機控制該晶元的低相位噪聲頻率合成器的設計方法，討論了環路濾波器的設計，為高頻頻率合成器的設計提供了很好的思路。Thus, the better phase noise can be obtained by adjusting the loop wave filtering. through experimental verification, the locking range of the designed ka band ilpll circuit is 2. 5 times to 9 times widened and the phase noise, compared to that without feedback loop, is reduced by 4dbc @ 1khz and the noise can be reduced by adjusting the loop wave filtering and
經過實驗驗證，設計的ka波段ilpll電路的鎖定帶寬拓展了2 . 5倍以上，最大處達到9倍左右;相噪與開環注鎖相比降低了4dbc @ 1khz ，且可以通過調節環路濾波和注入功率來降低噪聲。分享友人