硅晶體管 的英文怎麼說

中文拼音 [guījīngtǐguǎn]
硅晶體管 英文
silicon tra istor
  • 硅 : 名詞[化學] silicon （14號元素符號 si）
  • 晶 : Ⅰ形容詞（光亮） brilliant; glittering Ⅱ名詞1. （水晶） quartz; （rock） crystal 2. （晶體） any crystalline substance
  • 體 : 體構詞成分。
  • 管 : Ⅰ名詞1 （管子） pipe; tube 2 （吹奏的樂器） wind musical instrument 3 （形狀似管的電器件） valve;...
  • 晶體 : [晶體學] crystal; vitrella; crystal body; crystalloid; x-tal
  1. Semiconductor discrete device. detail specification for pnp silicon low - power transistor for type 3cg110gp gt and gct classes

    半導體分立器件gp gt和gct級3cg110型pnp硅小功率晶體管.詳細規范
  2. Semiconductor discrete device. detail specification for npn silicon high - frequency low - power transistor for type 3dg130gp gt and gct classes

    半導體分立器件gp gt和gct級3dg130型npn硅高頻小功率晶體管.詳細規范
  3. Semiconductor discrete device. detail specification for npn silicon low - power hiht - reverse - voltage transistor for type 3dg182gp gt and gct classes

    半導體分立器件gp gt和gct級3dg182型npn硅小功率高反壓晶體管.詳細規范
  4. Semiconductor optoelectronic devices. delail specification for type gt16 si. npn phototransistor

    半導體光電子器件gti6型硅npn光電晶體管詳細規范
  5. Device degradation behaviors of typical - sized n - type metal induced lateral crystallized polycrystalline silicon thin film transistors were investigated under two kinds of dc bias stresses : hot carrier stress and self - heating stress

    本文主要研究了典型尺寸的n型金屬誘導橫向結晶多晶硅薄膜晶體管在兩種常見的直流應力偏置下的退化現象:熱載流子退化和自加熱退化。
  6. N - channel silicon planar epitaxial jfet

    通道硅平面型外延接面型場效晶體管
  7. Abstract : a vertical sandwich deep trench with a field limiting ring is proposed to improve the breakdown voltage of power devices and high voltage devices. simulation result shows that nearly 100 breakdown voltage of the plane junction can be realized

    文摘:提出一種二氧化硅/多晶硅/二氧化硅夾心深槽場限制環新結構來提高晶體管的擊穿電壓.模擬結果顯示，該結構可以使射頻功率雙極性晶體管的擊穿電壓幾乎100達到平行平面結的理想值
  8. Placing a thin layer of insulation between the silicon surface and the transistors protects the transistors from " electrical effects, " leading to higher performance and lower power consumption

    在硅表面之間放上很薄的一層絕緣體，可以防止晶體管的「電子效應」 ，這樣可以實現更高的性能和更低的功耗。
  9. Wirings of the poly layer are always utilized under the silicon grid technics. to control the macro - cell signal delay and improve signal integrality, the crossing among different nets must be averagely distributed to reduce the number of layer permutation. the metal layer wirings should be maximized and the length of poly layer wiring in each net should be minimized

    硅柵工藝晶體管級布線利用多晶層走線，為了控制宏單元時延性能及改善信號完整性形態，關鍵是不同線網間交叉的均衡分配以減少走線的換層次數，最大化金屬層走線以及每一線網多晶層走線長度的有效控制。
  10. Ti introduces the silicon - based transistor which soon eclipsed germaninum devices in production volume

    Ti公司開發硅晶體管，從而在生產量上迅速超過鍺晶體管。
  11. After constructing a 35 - nanometer - high channel between two silica plates and filling it with potassium chloride saltwater, they demonstrated that voltage applied across this nanofluidic transistor could switch potassium ion flow on and off

    他們在兩片硅板之間製作35奈米高的通道，注入氯化鉀溶液，示範在這個奈米流體晶體管上施加的電壓可開啟或阻斷鉀離子流。
  12. Detail specification for electronic components. case rated bipolar transistor for silicon npn high - frequency amplification for type 3da1162

    電子元器件詳細規范. 3da1162型硅npn高頻放大管殼額定的雙極型晶體管
  13. Detail specification for electronic components. case rated bipolar transistor for silicon npn high - frequency amplification for type 3da1722

    電子元器件詳細規范. 3da1722型硅npn高頻放大管殼額定的雙極型晶體管
  14. Detail specification for electronic components. case rated bipolar transistor for silicon npn high - frequency amplification for type 3da 2688

    電子元器件詳細規范. 3da2688型硅npn高頻放大管殼額定的雙極型晶體管
  15. Along with silicon ulsi technology has seen an exponential improvement in virtually any figure of merit, as described by moore ’ s law ; the miniaturization of circuit elements down to the nanometer scale has resulted in structures which exhibt novel physical effects due to the emerging quantum mechanical nature of the electrons, the new devices take advantage of quantum mechanical phenomena that emerge on the nanometer scale, including the discreteness of electrons. laws of quantum mechanics and the limitations of fabrication may soon prevent further reduction in the size of today ’ s conventional field effect transistors ( fet ’ s )

    隨著超大規模集成電路的的發展，半導體硅技術非常好地遵循moore定理發展，電子器件的特徵尺寸越來越小;數字集成電路的晶元的集成度越來越高，電子器件由微米級進入納米級，量子效應對器件工作的影響變的越來越重要，尺寸小於10nm將出現一些如庫侖阻塞等新特性。量子效應將抑制傳統晶體管fet繼續按照以前的規律繼續減小。在這種情況下，宏觀的器件理論將被替代，可能需要採用新概念的晶體管結構。
  16. Specification for silicon epitaxial wafer for microwave power transistor

    微波功率晶體管用硅外延片規范
  17. Semiconductor discrete device. detail specification for silicon n - channel deplition mode field - effect transistor of type cs146

    半導體分立器件. cs146型硅n溝道耗盡型場效應晶體管.詳細規范
  18. Semiconductor discrete device. detail specification for type cs141 silicon n - channel mos deplition mode field - effect transistor

    半導體分立器件. cs141型硅n溝道mos耗盡型場效應晶體管詳細規范
  19. Semiconductor discrete device. detail specification for type cs140 silicon n - channel mos deplition mode field - effect transistor

    半導體分立器件. cs140型硅n溝道mos耗盡型場效應晶體管.詳細規范
  20. Semiconductor discrete device. detail specification for type cs5114 cs5116 silicon p - channel deplition mode field - effect transistor

    半導體分立器件. cs5114 cs5116型硅p溝道耗盡型場效應晶體管詳細規范
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