硬接線邏輯 的英文怎麼說

中文拼音 [yìngjiēxiànluó]
硬接線邏輯 英文
hardwired logic
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 接 : Ⅰ動詞1 （靠近;接觸） come into contact with; come close to 2 （連接; 使連接） connect; join; put ...
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 接線 : 1 [電學] （連接導線） wiring2 （電話員接通線路） work a telephone switchboard; connection接線插座...
  • 邏輯 : logic
  1. Therefore, it can be named by “ the specific demultiplexer of sdh ”. the design of pos line card was discussed and we also have finished the control logic of the hardware platform of the specific demultiplexer

    論文主要討論專用分接器的pos線卡設計和硬體平臺的控制邏輯電路設計與實現。論文首先對基於fpga的10gbps的pos線卡的設計方案進行了研究。
  2. A testbench program is edited to simulate the behavior of the fifo. after the software simulation is accomplished, a real hardware circuit is designed to multiplex two data channels ( 1553b data channel and 1394 data channel ) according to ccsds standard. during the experiment and hardware debugging, the output logic of the fpga is checked up

    設計中，用vhdl語言對高速復接器進行行為級建模，為了驗證這個模型，首先使用軟體進行模擬，通過編寫testbench程序模擬fifo的動作特點，對程序輸入信號進行模擬，在軟體邏輯模擬取得預期結果后，繼續設計硬體電路，設計出的實際電路實現了將來自兩個不同速率的信源數據（ 1394總線數據和1553b總線數據）復接成一路符合ccsds協議的位流業務數據。
  3. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡單的論述了pc並口協議（ epp ）與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上，給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶元hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計，其中，對數據緩沖電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖，包括軟體的基本要求和功能的設計與實現;接著從埠譯碼單元、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後，給出了測試結果，對研製工作做了總結，對本設計的優缺點各做了評述。
  4. Pipelining and parallel technology, accompanying with fast fifo as cache memory, instead of direct program operation, are adopted in the scheme and increase the transmitting speed dramatically ; fpga ( field programmable gate array ) is applied to realize the complex control logic of the system and makes it integrative, flexible and fast ; 386ex based embedded system, along with vxworks real - time operating system is introduced to substitute the microcontroller based system to simplify the hardware design and enhance the overall performance of ssr, and will make the system more easier to be applied to the projects in the future

    該設計方案採用了流水線和并行技術，配以快速fifo緩存的方式取代了直接對flash進行編程的方式，極大地提高了閃存晶元存儲數據的速率；採用fpga技術實現系統的主要控制邏輯，集成度高、靈活性好、速度快；採用基於386ex的嵌入式系統及基於vxworks的嵌入式實時操作系統，取代單片機系統及其編程，提高了系統的整體性能，減輕了硬體設計的負擔，且使系統研發的延續性好。
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