硬體加速器 的英文怎麼說
中文拼音 [yìngtǐjiāsùqì]
硬體加速器
英文
hardware accelerator-
In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical
在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。This paper starts the research of the liquid floated pendulous accelerometer testing system according to the engineering. at first, this paper gives the brief introduction of the history and present status of accelerometer and its testing technology, the working principium and math model of the liquid floated pendu - lous accelerometer, and then, decides the binary width pulse force retrim loop as the design proposal of testing system, researches the transfer function of every part in the system emphasizly, analyses the stability of the whole accelerometer testing system from the angle of control theoretics by the open loop transfer function of system, and designed the correcting net, analyses the basal problems such as resolution, sampling restraint, precision and so on, designs the hardware testing circuits such as preamplification, band - pass filter, alternating amplifier, phase sensitive demodulatorn, pulse - width modulation, frequency scale circuit, moment current generator. finally, using the graphics program language labv - iew which is designed for testing field especially by ni accomplishes the solfware design of testing system, realized the testing functions
首先對加速度計及其測試技術的發展歷史和現狀，液浮擺式加速度計的工作原理和數學模型等作了簡要的介紹，然後確定了以二元調寬脈沖再平衡測試迴路為設計方案，並從控制理論的角度進行了分析，著重研究了系統中各部分的傳遞函數，利用系統開環傳遞函數分析了系統的穩定性，同時設計了系統的校正網路;分析了二元調寬脈沖再平衡測試迴路的解析度、采樣約束以及測試精度等基本問題，並按照系統分析的結果設計了包括前置放大、帶通濾波、交流放大、相敏解調、脈寬調制、頻標電路以及力矩電流發生器等測試系統各部分硬體電路，驗證了電路的正確性，最後按照測試系統的要求，採用了美國ni公司專為測試領域所開發的虛擬儀器工具? ? labview作為測試軟體開發工具，利用該圖形化編程語言完成了測試系統軟體部分的設計，實現了測試功能。Due to the hardware characteristic ' s limitation, such as the poor speed of a / d, d / a conversion and dsp process, the most part of sr system adopt middle course. that is to say, by using the special digital converter or running relevant arithmetic, it converts the radio signal to intermediate frequency signal and completes the base - band signal process that is n ' t the veriest sr and is named " software defined radio ( sdr ) "
由於受到硬體性能如a d 、 d a及dsp晶元處理速度的限制，目前的軟體無線電系統多採用折中的實現方案，增加專用的數字變頻器或者運行數字變頻演算法，將射頻信號變頻到中頻，然後再進行基帶信號處理，這樣的軟體無線電系統又被稱之為「軟體定義無線電」 ，它並不是真正意義上的軟體無線電。In fact, no specifications or documentation have ever been released for any macintosh hardware, most notably the adb controller used by the mouse and keyboard, the floppy controller, and all acceleration and clut manipulation of the video hardware though we do now support clut manipulation on nearly all internal video chips
事實上， macintosh硬體沒有公布任何規格書與文檔，特別是adb控制器用於鼠標和鍵盤軟盤控制器所有的視頻硬體加速和clut處理器雖然我們不支持絕大多數內置顯示晶元的clut處理器。In such background, this thesis hope to develop and designs a series of applying in the military, the automobile and other domains test systems by researching the dsp and the mems inertial sensor, . this thesis mainly include following facets : the thsis designed a new type of four central suspension beams structure hardware electric circuit with the reference of adxl203 and carried on the electric circuit simulation
在這樣的背景下，本論文課題希望通過對dsp和mems慣性傳感器的研究，研製和設計出一系列能夠應用於軍事，汽車或者其他領域的測試系統。主要進行了以下工作:設計了一種全新的四梁中心懸臂結構加速度傳感器的硬體電路，並進行了電路的模擬。In chapter 5 we discuss the design of ieee754 standard fpu ( floating point unit ). processor and uart ( universal asynchronous receiver transmitter ), these cores are used in this dissertation, fpu is used for floating point complex fft processor, uart is used for fft processor " s peripheral and our test platform. in chapter 6 we discuss the design for testability, including atpg, bist and jtag method, discuss the different verification and simulation strategy in soc scale facing to different modules, build up the test platform which is used to test high performance application specified digital signal processing processor. in chapter 7 we summarize the research results and creative points, and point out the further work need to do in the future
第五章提出了基於ieee754浮點標準的浮點運算處理器的設計和異步串列通信核的設一浙江大學博士學位論文計，提出了適合硬體實現的浮點乘除法、加減運算的結構，浮點運算處理器主要用於高速fft浮點處理功能，異步串列通信核主要用於pft處理器ip核的外圍擴展模塊以及本文所做的驗證測試平臺中的數據介面部分第六章提出了面向系統級晶元的可測試性設計包括了基於掃描測試atpg 、內建自測試bist 、邊界掃描測試jtag設計，在討論可測試性設計策略選擇的問題上，提出了針對不同模塊進行的分別測試策略，提出了層次化jtag測試方法和掃描總線法，提出了基於fpgaIt ' s also a lot faster in case your second monitor doesn ' t have hardware acceleration, because technically, the rendering only happens off - screen on the first monitor ' s device
與此同時，由於你的第二個顯示器不需要硬體加速，這個辦法還能讓你的機器快很多。因為從技術上說，渲染過程只在第一個顯示設備外悄悄進行。Weca is also preparing to introduce aes, the latest security protocol, but which so far requires additional hardware acceleration for encryption using a coprocessor - something mobile devices have so far lacked
Weca還準備引入最新的安全性協議aes ，但aes至今還需要通過使用協處理器來對加密進行額外的硬體加速目前的移動設備還沒有這一功能。The designed model is compiled into custom instruction of nios processor via sopc interface, and made up hardware accelerator interface model
最後將該模塊通過sopc介面編輯成nios處理器的用戶指令，組成硬體加速器介面模塊。Through the fundamental research of the blade destruction, the digital filter software, the monolithic integrated circuit system software and hardware, the vibration acceleration sensor realizes the vibration protection together
通過對葉片破壞形式的理論研究，由數字濾波軟體、單片機系統軟硬體、振動加速度傳感器共同實現振動保護。As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost
所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。- the focal point of this paper is studying the problem of cargoes ? weight measurement, besides the component of mechanical system, the component and control of electric - control system, the full - digital dc speed adjustment system and the hardware and software design of plc control system. this paper puts forward the project of current static measurement method and corrects it with acceleration dynamic measurement
本文除分析介紹了集裝箱橋吊的機械繫統組成、電控系統的組成及控制、全數字直流調速器以及plc控制系統的軟硬體設計外，重點研究了集裝箱裝卸橋中的貨物稱重問題，提出了應用電流靜態測量法的稱重方案，並且採用了加速度動態測量法對其進行動態校正，在實際應用中取得了令人滿意的效果。The paper essentially research application of computer graphics processing and simulation of object oriented technique at visual emluator of drilling simulator. and stressfully research computer graphics processing together with give part realization. elaborating characteristic of graphics processing based on opengl, and give the three means of realization of opengl : software implementation, hardware realization and graphics accelerate mode, and has been penetrated into the acquirement to the architectural structure of opengl
本文重點研究了計算機圖形處理和面向對象的模擬技術在鉆井模擬器可視化模擬上的應用。對計算機圖形處理進行了較為詳盡的研究並給出了部分實現；詳細闡述了基於opengl的圖形處理的特點，給出opengl的三種實現方式：軟體實現、硬體實現和三維圖形加速模式，並對opengl的體系結構進行了深入探討。The viterbi decoder with hard decision designed by the paper, is aimed at ( 3, 1, 9 ) convolutional coding. the data rate is 9. 6kbps. the data rate received by the rake receiver is spreaded by 127 - bit spread sequences, added pilot signals and modulated by qpsk
該課題所設計viterbi譯碼是針對（ 3 ， 1 ， 9 ）卷積碼的硬判決譯碼，數據速率為9 . 6kbps ; rake接收機所接收的數據是擴頻因子為127 、加入導頻且經qpsk調制的擴頻信號，使用verilg硬體描述語言在xilinx公司的ise環境下在用現場可編程門陣列（ fpga ）來實現viterbi譯碼器和rake接=收機的功能。Because direct torque control requires very high performance of real - time, the popular microcomputer core dsp is used as controller in the design of hardware. its high speed of running is suitable for the experiment. in the main circuit, there is a highly integrated power element : ipm as inverter, which includes seven igbt, has high switch frequency and fault diagnosis function
在本控制系統的具體實現上，由於直接轉矩控制對實時性要求很高，因此在硬體方面，採用了目前比較流行的數字信號處理器（ dsp ）作為系統的控制器，其處理速度高的特點正好符合本實驗的需要：在主電路中，本系統使用了集成度高的功率器件：智能功率模塊（ ipm ） ，作為逆變環節，其集成了七個igbt ，實現了高開關頻率逆變以及故障診斷的功能，從而使控制系統的體積大大縮小、控制更加靈活。Due to the direct torque control requires very high performance of real - time, the popular microcomputer core dsp is used as controller in the design of hardware. its high speed of running is suitable to the experiment. in the main circuit, there is a highly integrated power element : ipm as inverter, which includes seven igbt, has high switch frequency and fault diagnosis function
在本控制系統的具體實現上，由於直接轉矩控制對實時性要求很高，因此在硬體方面，本課題採用了目前比較流行的數字信號處理器（ dsp ）作為本實驗的控制器，其處理速度高的特點正好符合本實驗的需要；在主電路中，本系統使用了集成度高的功率器件：智能功率模塊（ ipm ） ，作為逆變環節，其集成了七個igbt ，實現了高開關頻率逆變以及故障診斷的功能，從而使控制系統的體積大大縮小、控制更加靈活。Durning study of the subject, realizating comprehensive rf front - end simulator and starfabric data - distributed interface module in hardware. moreover, it elaborates the achievement of a system of data - distributed based on starfabric technology, by designing hardware modules, multi - entrance high - speed switch module, signal processing module and pc terminal
在課題研究期間，在硬體上完成了高速數據分發系統中的綜合射頻前端模擬器和starfbric數據分發介面板設計及實現，並用所設計的硬體模塊，加上多埠高速交換模塊、信號處理模塊和pc終端實現了一個基於starfabric技術的高速數據分發系統。A vlsi very large scale integration architecture is also proposed to implement the improved motion estimation algorithm. experimental results show that this algorithm - hardware co - design gives better tradeoff of gate - count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in avs
考慮到avs主要面向圖像尺寸較大的高清數字電視壓縮，這種高復雜度的運算已經超過了現有通用處理器的運算能力，因此有必要設計專門的快速演算法和與這種演算法相匹配的硬體加速器。A hybrid client - server structure for transmitting terrain images and models is suggested, and the scheme of corresponding transmission system is proposed. the design and implementation of a hardware accelerated 3d electronic map system is described ; capabilities, components and structure, implementation and runtime snapshots of the system are also covered
提出了傳輸地形圖像和地形模型的組合式客戶-服務器結構以及相應的傳輸系統方案；描述了一個基於硬體加速的三維電子地圖系統的設計和實現，介紹了它的功能、組成結構、實現以及運行實例。Specifies whether a hardware - accelerated device type can be used on the current adapter
指定在當前適配器上是否可以使用硬體加速的設備類型。分享友人