硬體模擬程序 的英文怎麼說

中文拼音 [yìngtǐmónǐchéngxù]
硬體模擬程序 英文
hardware emulator
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 模 : 模名詞1. （模子） mould; pattern; matrix 2. （姓氏） a surname
  • 擬 : 動詞1. （設計; 起草） draw up; draft 2. （打算; 想要） intend; plan 3. （模仿） imitate
  • 程 : 名詞1 （規章; 法式） rule; regulation 2 （進度; 程序） order; procedure 3 （路途; 一段路） journe...
  • 硬體 : hardware
  • 模擬 : imitate; simulate; analog; analogy; imitation; simulation模擬艙 boilerplate; 模擬電路 [電學] circ...
  • 程序 : 1 （進行次序） order; procedure; course; sequence; schedule; ground rule; routing process 2 [自動...
  1. Pressure sensor and hygrothermograph sensor are adopted respectively to sense these change ; a plc and its analogue cell are adopted to collect and analysis the data ; a mcgs component software is used to process and store the data in real time

    給出了以壓力、流量和溫濕度傳感器為測量元件、以plc為主控制器、 plc模擬單元為數據轉換單元的詳細硬體設計、程序設計和組態軟體mcgs在上位機的運用。
  2. Finaiiy, the paper also has introduced the virtua1 worid of windows rs ; j { ? # - - lase / and how to map the 1ogica1 address to physica1 address in protected mode and the interrupt mechanism of protected mode, then the paper has i11ustrated that it is necessary to write virtua1 device driver ( vxd ) in order to access hardware device from the third leve1

    最後，在介紹了windows的虛擬世界，和在保護模式下如何將邏輯地址映射成物理地址，以及保護模式下的中斷機制的基礎上，闡明了在保護模式下應用程序對硬體設備操作驅動程序的必需的中間橋梁作用。
  3. In the hardware design, the paper completes modules ’ design like outside memory, patulous a / d, patulous d / a, rs232 communication, ecan communication, led control, keyboard control, distant control, emulation, reset, logic voltage switch, dsp supply power regulate and ac - dc power circuit, as well as room layout design like anterior panel, back panel etc. and dsp transfers data with peripheral equipments except outside memory using serial ports. besides, the whole circuit is configured in interrupt response. thus, it can meet system demand as well as take full advantage of tms320f2812 ’ s hardware resource. in the software design, the paper finishs programs like the interface programms intercommunicates with people, the distant control program, ad and da modules ’ control program, in addition, the paper select the velocity and acceleration state - feedback algorithm and is written in the program. the software design uses dsp integrate exploiting environment named ccs2. 2 of ti inc. as software instrument, and programs with the combination of c language and assembly language. moreover, in order to maintenance or modify the software expediently and shorten software ’ s exploitation time, the design adopt software modularization technique. finally, some air cylinder experiments are carried out to proved that the pneumatic controller is very practical

    在硬體設計中，本文完成了片外存儲器擴展、 a / d擴展、 d / a擴展、 rs232通信介面、 ecan通信總線介面、液晶顯示控制、鍵盤控制、遠程控制、模擬、復位、邏輯電平轉換、 dsp工作電源校正電路和ac - dc電源等模塊設計以及控制器前面板、後面板等的空間布局設計。其中dsp與除外部存儲器的外圍設備之間的數據傳送全部採用串口通信，同時系統電路配置成中斷響應方式，這樣既滿足了系統要求，又充分利用了tms320f2812的硬體資源。在軟體設計中，本文完成了人機界面功能模塊、遠程控制模塊、 ad擴展模塊、 da擴展模塊、速度和加速度狀態反饋的控制演算法的程序設計。
  4. In this equipment, a mcu controller is responsible for digital image acquisition, realized stable data transmission between different running frequency units. the whole algorithm is simulated and optimized on dsp evm board and ccs environment, which contribute to a seamless software transplant and hardware structure design

    通過中斷機制，實現數據的可靠傳輸，在dspevm板環境下，對演算法程序進行優化和比較，完成演算法模擬測試，實現軟體無縫移植和硬體的結構化設計。
  5. Finally, basing on the above theory research and the existing hardware scheme, the optimization probabilities is discussed among the layers of the standard entrails, arithmetic promotions and program optimizations. the optimizations are carried out in the software simulation circumstance, and obtain a notable effect, which boosts the coding speed by 60 % with the same image quality, showing an applying prospect

    最後，在以上的理論研究基礎上，結合現有的硬體方案，從標準內部、演算法改良和程序優化等多個層面上探討了對視頻編解碼系統的優化可能，並在軟體模擬的環境下付諸于實踐，取得了明顯的效果，在保證圖像質量的前提下，將編碼速度提高了約60 % ，顯示出了一定的實際應用前景。
  6. Firstly the dissertation describes the hardware and software architecture, and shows the goal of this design. from requirement analysis to modules implementation, the dissertation gives the whole vision of the development process. secondly, it describes the low level layer implementation

    本文重點闡述了數字示波表的整體框架設計，圖形界面介面設計，內存管理設計，消息隊列管理以及底層硬體驅動程序和部分功能的實現，同時還說明了高級語言級別的軟體模擬系統設計和實現。
  7. The amount used is significantly lower if you use ibm s synchronous data compression hardware feature than if you use the db2 software simulation program when db2 is started, it determines whether or not the hardware compression feature is available

    與使用db2軟體模擬程序相比，使用ibm的同步數據壓縮硬體可以大大減少所消耗的cpu資源（當db2啟動時，它將判斷硬體壓縮特性是否可用） 。
  8. It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function

    本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。
  9. The circuit is synthesized by synplify pro which is synplicity ' s synthesis tool and emulated by quartus ii which is altera ' s developing tool, which has proved the feasibility and correctness of the circuit

    採用硬體描述語言vetilog編寫了硬體電路程序，並使用synplicity的綜合工具synplifypro和altera開發工具quartus對電路系統進行了綜合與模擬驗證，證明了硬體電路的可行性與正確性。
  10. As the 3rd generation computer - assisted digital measurement and testing instrumentation, virtual instrument is the outcome accomplished with the development of electronics technology, measurement and testing technology, and computer technology, moving toward bus and driver standardization, programming platform graphics, hardware and software modularization, and hardware plug and play

    作為第三代基於計算機數字化測量測試儀器技術的虛擬儀器（ virtualinstrument簡稱vi ）是電子技術、測試技術和計算機技術綜合集成的產物。它正沿著總線與驅動程序標準化、硬軟體模塊化、編程平臺圖形化和硬體模塊的即插即用方向前進。
  11. Real time hardware simulation and automotive test are done. test and simulation results are compared. the conclusion testifies models and fuzzy control algorithm are correct, and algorithm can be improve continuously

    將基於智能權的模糊控制演算法轉化為c程序，並進行實時硬體模擬和實車試驗，將兩者的結果與控制演算法模型模擬結果進行對比分析，得出結論，證明所建模型和演算法的正確，且在控制演算法上仍有改進的餘地。
  12. 1 ) realization of software packet embedded in m - es and md - is respectively to accomplish main function of mdlp, including assignment of tei ( temporary equipment identifier ), establishment of multiple frame operation, framing, flow control and error - free transmission of packets, is detailed. 2 ) a test model is established to evaluate the robustness and stability of mdlp and verify the validity of software packets. 3 ) according to the design of radio modem construction used in m - es, the modules of interface between data terminal equipment and radio modem are achieved to enable transmission of short message and continuous pseudo - random bit stream via rs232 uart

    本文首先概述了蜂窩數字分組數據網的結構和空中協議，詳細分析了移動數據鏈路協議，並在此基礎上，重點敘述了以下方面的工作： 1 ）設計並完成了分別應用於m - es和md - is端無線控制器的兩套程序實現數據鏈路層的主要功能，包括分配臨時設備號、建立鏈路、組幀和面向連接的服務保證分組正確無誤地傳輸，並進行適當的流控； 2 ）建立測試模型測試移動數據鏈路協議的可靠性和穩定性，證明了程序包的效用； 3 ）根據cdpd系統無線數據機的軟硬體總體設計方案，完成了介面模塊，實現了rs232異步串口通信，使用戶可以根據需要發送短消息或連續的偽隨機比特流； 4 ）在tms320c54x的軟體、硬體模擬平臺上，建立了cdpd試驗模型，實現了cdpd系統的mdlp基本功能。
  13. The paper puts forward a kind of economical numerical control milling machine system which is supported by windows and industry pc that are acted as software and hardware platform on the base of analyzing the present development of economical numerical control system and some existent problem, and expatiates the system software ' s collectivity frame, also introduces detailedly form and operational way of the user ' s interface. besides, the thesis also frames and accomplishes each module such as syntax inspect module, translation module, tool compensation module and track interpolation module adopting visual c + + 6. 0 and the kind of facing object and modularized program design method by analyzing rationales and function of the software ' s modules, moreover presents the programmer ' s flow chart and parts of source code, whereafter validates arithmetic of translation and tool compensation by simulating process testing program

    本文在分析了我國經濟型數控系統的發展現狀以及目前存在的一些問題的基礎上，提出了一種以windows和工業pc機作為軟、硬體平臺的經濟型數控銑床系統，闡述了該系統軟體的總體結構，並對其用戶界面的組成及其操作過程做了較為詳細的介紹，分析了軟體的各個模塊的基本原理和功能，採用visualc + + 6 . 0以及面向對象、模塊化的程序設計方法，完成了語法檢查模塊、譯碼模塊、刀具補償模塊以及軌跡插補模塊的具體設計，並給出了程序設計流程圖和部分源代碼，通過系統的模擬程序模擬加工過程驗證了譯碼和刀補演算法的正確性。
  14. And software simulator is used to simulate the behavior of the program running on the real chip with software. the simulator can not only bring convenience to the user of the chip, but also make the software developing synchronous with the design of hardware

    軟體模擬器對用軟體來模擬應用程序在目標晶元上的行為，用高級語言強大的表達力來模擬晶元的功能，不僅能為晶元的用戶帶來便利，而且能使晶元的設計者在晶元硬體設計的同時進行軟體開發，以驗證晶元的結構。
  15. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
  16. This is one kind project of hardware multiplexer based on the high - performance system on a programmable chip ( sopc ). in the project author integrate with the software and the hardware on a field programmable gate array ( fpga ), not only simplifying the overall system design, moreover realizing stably, high speed, low cost multiplexer ’ s design. the dissertation carry on three verification step that include function verification 、 time verification and prototype verification to guarantee each ip can work normally to satisfy the system performance requirement. then author introduce the realization of the multiplexer in detail, as well as the test and the debugging questions met in practice and solution of the questions

    本方案是一種基於可編程片上系統（ sopc ）的硬體復用器設計方案，其特點是將系統的軟體和硬體集成在一款現場可編程門陣列（ fpga ）上，使用該方案不但簡化了整個系統，而且實現了穩定、高速、低成本的復用器設計。對系統中各個功能模塊的整合和驗證採用功能模擬、時序模擬、原型驗證三個步驟進行，保證系統中各個功能模塊可以正常工作，並滿足系統的性能要求。然後詳細介紹了復用器的實現，以及測試和調試中遇到的問題及解決方法。
  17. Full hardware emulation is especially common for accessing older - machine programs

    完全硬體模擬常用於使用較老機器的程序。
  18. This dissertation finishes the design of pci bus target controller, with vhdl description of register transfers level. and it has also completed the function simulation as well as timing simulation after placing & routing. a fpga on pcb board is designed to test the target controller and the result of test meets basal function demand

    本論文完成了pci總線目標設備控制器的設計，採用vhdl對其進行了rtl級的描述，並且通過編寫測試激勵程序完成了功能模擬，以及布局布線后的時序模擬，通過fpga在pcb實驗板上進行硬體模擬，證明所實現的pci目標設備控制器符合基本功能要求。
  19. Although the smart device emulators can be used in almost all stages of development, testing your application on a real - world piece of hardware is a vital part of the development cycle

    盡管幾乎可以在開發過程的所有階段使用智能設備模擬程序，但是在實際硬體上測試應用程序是開發周期中不可或缺的重要組成部分。
  20. They commonly run simulations and other cpu - intensive programs that would take an inordinate amount of time to run on regular hardware

    高性能集群通常會運行一些模擬程序和其他對cpu非常敏感的程序，這些程序在普通的硬體上運行需要花費大量的時間。
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