硬體設計語言 的英文怎麼說

中文拼音 [yìngtǐshèjìyǔyán]
硬體設計語言 英文
hardware design language
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 設 : Ⅰ動詞1 （設立; 布置） set up; establish; found 2 （籌劃） work out : 設計陷害 plot a frame up; fr...
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 語 : 語動詞[書面語] （告訴） tell; inform
  • 言 : Ⅰ名詞1. （話） speech; word 2. （漢語的一個字） character; word 3. （姓氏） a surname Ⅱ動詞（說） say; talk; speak
  • 硬體 : hardware
  • 設計 : devise; project; plan; design; excogitation; layout; layout work; styling
  • 語言 : language
  1. Thus, the vhdl is carried to make a design for the forenamed algorithms, and the design is validated by simulation

    因此，本文用vhdl語言實現了ca邊緣檢測演算法模型的基本內核設計，並通過時序模擬，進行了演算法的硬體設計與效果驗證。
  2. Digital image processing consume a large amount of memory and time commonly. basing on the advantage of fpga, the paper design harware module by hdl ( hardware language ), i. e., some function is achieved by les ( logic element ) of the fpga. the real - time of digital image processing is achieved by this. the sample and display of digital image is the important part. so, the paper mainly design the sample and desplay module. the sample card is designed and it ’ s word mode is configured according china ’ s cvbs ( composite video bar signal ). for acquiring the image and storing it correctly to sram, the paper design the sample - control module. the sample module can work correctly using least time. the reliability and real - time achieve the reference. according the vga principle and scheduling of the ths8134, the paper design a vga - control module by hdl. firstly, the control signal is synthesized secondly, the horirontal and vertical synchronization signals is synthesized according to the vga interface standard

    圖像處理的特點是處理的數據量大，處理非常耗時，為實現數字圖像的實時處理，本文研究了在fpga上用硬體描述語言實現功能模塊的方法，通過功能模塊的硬體化，解決了視頻圖像處理的速度問題。圖像數據的正確採集和顯示輸出是其中的兩個重要的模塊，因此，本文主要完成了圖像數據的採集和顯示輸出的設計。本文設計了採集卡，並要對其工作模式進行了配置和編寫了採集控制模塊，在採集控制模塊的控制下，將數字圖像數據正確無誤的存儲到了sram中。
  3. Thi s dissertation first describes syntax, semanteme and method of modeling hardware of veri1og hdl and vhdl in detai1 so that strong abi1 ity of designing and simu1ating waveform is represented in hardware circuits

    本文首先對兩種硬體描述語言veriloghdl和vhdl在語義、語法及硬體建模方法進行了詳細的描述，說明它們在硬體電路波形表示方面有較強的設計與模擬能力。
  4. It is an important character that using hdl describes function and behavior of logic device or system hardware

    使用硬體設計語言來描述邏輯器件及系統硬體的功能和行為是硬體描述語言編程設計方法的一個重要特徵。
  5. Because period narrow band signals are the main part of background noises, this thesis uses hardware description language to design a multi - band finite impulse response filter ( fir ) and downloads the program into filed programmable gate array to eliminate the period narrow - band interferences in the background noises

    3 ）在現場環境中，背景干擾主要是周期性的窄帶，本文利用硬體描述語言（ vhdl ）設計了一個多帶fir有限沖擊響應濾波器。應用到可編程邏輯器件中，消除了背景噪聲中的周期性干擾，為信號的進一步處理提供盡可能幹凈的信號。
  6. In this paper, using a top - down design scheme, the risc mcu ip core is divided into two parts : data path and control path. all the modules in the two parts are described by verilog hdl, a kind of hardware description language. the simulation and synthesis of the whole work are finished successfully with eda tools

    本文對pic16c6x單片機系統結構、指令系統和系統時序進行了分析，並且在此基礎上對精簡指令集mcuip核進行頂層功能和結構的定義與劃分，建立了一個可行有效的riscmcuip核模型本文將mcuip核劃分為數據通道與控制通道兩部分，採用asic設計中的高層次設計方法，使用硬體描述語言veriloghdl對這兩部分的各功能模塊進行了設計描述；利用多種eda工具對整個系統進行了模擬驗證與綜合。
  7. The whole correlation - inheritance coding circuit system is designed, simulated and verified in verilog hdl on the candence systems

    採用了硬體描述語言verilog對整個相關繼承矢量量化圖像編碼電路系統在cadence系統上進行了西安理工大學碩士論文設計、模擬及時序驗證。
  8. There are several aspects of work that was done in this thesis mainly. firstly, the theory of the under - water long - range remote control system was analyzed and the remote control instruction code was designed. secondly, decoding circuit of the under - water long - range remote control system was designed with fpga, including vhdl coding, simulation, synthesis, place & route, etc. besides, power consumption to fpga that is designed is estimated in this thesis. lastly, we designed and made one pcb to verify and test fpga decoding chip that is designed, and debugged and tested it finally

    首先，深入研究和分析了在頻域實現水下遠程遙控解碼的原理並進行了遙控指令編碼設計；其次，用altera公司的cyclone系列fpga晶元完成了水下遠程遙控fpga解碼晶元的設計工作，包括硬體描述語言（ vhdl ）編碼、電路前後模擬、綜合和布局布線工作，並對設計的fpga解碼晶元進行了初步的功耗估算；最後設計製作了一塊fpga解碼晶元電路驗證測試板，並完成了電路調試和測試。
  9. As a result, this design accomplishs the function of circuit, which not only can satisfy the high speed image data transmission of large screen system and improve the performance of circuit, but also increase the flexibility of circuit design. in the design, it is possible to act hardware description language procedure according to the practical application demand, instead of revising hardware design of the circuit, which reduce the design cycle and the cost

    所以，本課題運用可編程邏輯器件來完成電路功能，不僅能夠滿足大屏幕系統高速圖像數據傳輸對速度的要求，改善了電路性能，而且增加了電路設計的靈活性，設計中可以根據實際應用的需求靈活修改相應硬體描述語言程序，而不需要修改電路硬體設計，縮短了設計周期，降低了成本。
  10. The methods of adopting fpga to realize the function of counter, and adopting verilog hdl hardware description language to design every function modules, not only makes the whole design more compact and stable, but also make the alteration of the circuit ’ function merely need to alter the software according to the practical task requires, and needn ’ t alter the hardware connection of the circuit

    在計數器功能的實現上採用fpga （ fieldprogrammablegatearray ） ，利用veriloghdl （ hardwaredescriptionlanguage ）語言編寫了各個功能模塊，不僅使整個設計更加緊湊、穩定且可靠，而且可以根據實際的任務要求，在無需改變硬體電路板的情況下，通過修改硬體描述語言程序，即可修改電路功能。
  11. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  12. Besides the design of the hardware construction for shape meter, the software system written in visual basic 6. 0 is also developed. the real - time data acquisition and conversion system worked in interrupt mode is accomplished by means of loading dynamic linkage library of pcl - 812pg enhanced multi - lab card. the converted data processing will be operated then, for example, scale operation, comparison, graphic display, data storage, etc. the adjusting values for the shape control are also calculated in it

    本文在參考大量帶材標準板形、軋制初始量設定、調節量計算研究的基礎上，確定了標準板形模型、設定模型、調節控制模型等數學模型；並給出了其相應的演算法；完成了板形儀計算機控制系統的硬體設計，並在此基礎上，應用高級開發語言visualbasic6 . 0 ，通過加載pcl - 812pg多功能數據採集卡的驅動程序后，調用動態鏈接庫（ dll ）中的函數的方法，完成了信號中斷方式下的實時數據採集，採集的數據經計算機作標度變換、對比、圖形顯示、存儲等處理，並提供了用於板形閉環控制的調節量。
  13. Chosen the cvsd as the radio station ’ s voice coding. the character of strong anti - interfere in real communication circumstance was our major consideration to choose cvsd. as to validate the algorithm of cvsd and get the better parameter, we do the cvsd algorithm simulation firstly with matlab and the simulation tested the algorithm as well as given us some tips during the hardware debugging

    在實際設計和實現語音編碼過程中為了對硬體編程語言有好的指導作用以及得到比較好的編碼參數，首先用了matlab對語音編碼進行了模擬，通過模擬驗證了演算法同時獲得的參數為實際的硬體實現提供了一定的參考價值，也給我們的實際調試指出了方向性的指導。
  14. Then we explicate the hardware design in details, including implementing ad convert, extending multiple serial communications and external memory, and using cpld do some logic controls. thereby we implement abundance simulation interface, flexible digital interface and serial communication interface. at last we describe the software design, including software design of cpld basing on vhdl and software design of dsp

    本文首先介紹飛行模擬訓練系統的主要組成；接著說明飛控計算機整體系統方案的設計；然後詳細說明飛控計算機硬體平臺的設計，包括ad轉換、多串口通信、外部存儲器的擴展以及採用可編程邏輯器件cpld實現電路的邏輯控制等幾部分，體現了系統豐富的模擬介面、方便靈活的數字介面和串列通信介面；最後是軟體部分的編程，包括cpld部分的硬體描述語言程序設計，和dsp部分相關的程序設計。
  15. The whole design of on - line monitoring system is built in this subject, which system is based on data stream status, running characters, the requirements for in - situ monitor, communication technology and database knowledge. this system used graphic programming language labview for software developing tool and the production of rockwell for hardware

    根據高溫風機監測系統數據流量狀況、機組運行特點及現場監測要求，結合網路通訊技術和數據庫知識，以圖形化設計語言labview為開發平臺，以美國羅克韋爾自動化公司的硬體模塊為基礎，構建了在線監測系統的總體設計方案。
  16. Becausc of using the advanced dsp, popu1ar high speed pci bus and laxge scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree

    由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得本設計的整個系統具有相當的水平。
  17. Because of using the advanced dsp, popular high speed pci bus and large scale fpga, using vhdl hardware descriptive language to design the interface logic, the level of designed hardware is to a certain degree

    由於採用了先進的dsp處理晶元和結構、流行的高速總線pci總線、大規模fpga及vhdl硬體描述語言進行介面邏輯設計，使得整個系統具有相當高的數據處理能力。
  18. Electronic design hardware description language vhdl

    電子設計硬體描述語言vhdl
  19. 3 ) design switch system using eda based on the result of a11alysis. because the function of switch system is very complicated, some modules are designed by schematics directly, most modules are designed by verilog hdl using eda technology, synthesized by the synopsys software. at last a high speed atm switch system is designed, including voq as input buffer strategy dpa cell scheduling algorithm and crossbar switch fabric

    在前面分析的基礎上根據目前的條件，對一個空分交換系統各模塊進行前端設計和模擬，由於交換系統的功能復雜，我們一部分將採用直接畫原理圖的方法進行設計，大部分將採用集成電路設計自動化的方法進行設計，即採用硬體設計語言verilog ? hdl進行設計，用synopsys軟體對設計進行綜合，生成線路圖，然後作門級電路模擬。
  20. Specification for the representation of quality rules and metrics for hardware and software design languages

    軟體和硬體設計語言的質量規則和度量表示的規范
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