硬體語言 的英文怎麼說

中文拼音 [yìngtǐyǔyán]
硬體語言 英文
hardware language
  • 硬 : 形容詞1 （堅硬） hard; stiff; tough 2 （剛強; 堅定; 強硬） strong; firm; tough; obstinate 3 （勉...
  • 體 : 體構詞成分。
  • 語 : 語動詞[書面語] （告訴） tell; inform
  • 言 : Ⅰ名詞1. （話） speech; word 2. （漢語的一個字） character; word 3. （姓氏） a surname Ⅱ動詞（說） say; talk; speak
  • 硬體 : hardware
  • 語言 : language
  1. We implemented mentioned above functions with visual c + + 6. 0 language, developed software package, associated with designed hardware system, tested 8 kinds of common agricultural pest, for example, eterusia aedea linneus, parasa consocia, marumba aperchius, asparagus caterpillar, maize borer, cotton bollworm, army worm, and so on. rate of recognition is up to 85. 7 %. when it c

    用visualc什6 . 0語言實現了上述各環節的功能，開發了識別系統軟體包，與研製的硬體裝置相配合，分別對茶斑蛾、褐邊綠刺蛾、栗六點天蛾、甜菜夜蛾、玉米螟、棉鈴蟲、粘蟲等8種常見的農田害蟲進行測試，識別率達到了85 . 7 % 。
  2. The circuits driving the ccd and processing the video signal are implemented by means of cpld ( complex programmable logic device ) and hdl ( hardvvare description language ). the solution to solve the problem of multi - level logical competitive risks that occur in cpld circuits frequently was provided in details in the thesis

    Ccd的驅動電路和視頻信號處理電路採用cpld （可編程邏輯器件）和hdl （硬體描述語言）實現，文章對cpld電路中容易出現的多級邏輯冒險競爭情況作了專門的敘述和提出相應的解決方法。
  3. The paper studies and designs the circuit driving the servo motor and the motor for clearing, and the serial communication circuit, and the sensor data input circuit etc. the author develop the embedded controller software based the advanced singlechip language - pl / m and the user interface software base vc + + 6. 0

    進行了清刷機器人的伺服電機驅動與控制電路、清刷電機驅動與控制電路、串列通訊電路、傾角傳感器數據採集等硬體電路的設計，並進行了基於pl m高級單片機開發語言的下位機嵌入式控制軟體的開發和基於vc + + 6 . 0的上位機用戶操作界面的開發。
  4. After the methods of a / d and d / a were expressed according to the hardware and needs of the system, the article explains the language environment and the program structure

    在結合具體硬體環境和系統需求明確了系統的a d 、 d a等環節的實現手段以後，文章對系統控製程序所採用的具體的語言環境和程序結構進行了說明。
  5. According to the research, the major work done is as following : < 1 > analyzes the symmetric - key encryption algorithm des and dissymmetric - key encryption algorithm rsa, and makes them easy to realize in hardware. < 2 > according to the algorithms and the thought of reconfigurable computing, the dissertation accomplishes the design of 64 - bit des system architecture and the design of 256 - bit ~ 1024 - bit rsa system architecture. < 3 > using the top - down high level design methodology and the hdl language, accomplishes the description of the des / rsa designs, the simulation and the synthesis

    本論文主要的研究工作： < 1 >對現有的對稱加密演算法des演算法和非對稱加密演算法rsa演算法進行分析，使其易用硬體實現； < 2 >基於可重構思想和特點，完成64位des演算法和256位1024位模長rsa演算法的可重構硬體的設計； < 3 >採用自頂向下的設計方法，利用hdl語言對des / rsa設計進行功能描述，並完成軟體模擬，綜合和布線； < 4 >在可重構計算驗證平臺上進行演算法驗證，並對設計的可重構和設計的進一步優化進行討論。
  6. Thus, the vhdl is carried to make a design for the forenamed algorithms, and the design is validated by simulation

    因此，本文用vhdl語言實現了ca邊緣檢測演算法模型的基本內核設計，並通過時序模擬，進行了演算法的硬體設計與效果驗證。
  7. Digital image processing consume a large amount of memory and time commonly. basing on the advantage of fpga, the paper design harware module by hdl ( hardware language ), i. e., some function is achieved by les ( logic element ) of the fpga. the real - time of digital image processing is achieved by this. the sample and display of digital image is the important part. so, the paper mainly design the sample and desplay module. the sample card is designed and it ’ s word mode is configured according china ’ s cvbs ( composite video bar signal ). for acquiring the image and storing it correctly to sram, the paper design the sample - control module. the sample module can work correctly using least time. the reliability and real - time achieve the reference. according the vga principle and scheduling of the ths8134, the paper design a vga - control module by hdl. firstly, the control signal is synthesized secondly, the horirontal and vertical synchronization signals is synthesized according to the vga interface standard

    圖像處理的特點是處理的數據量大，處理非常耗時，為實現數字圖像的實時處理，本文研究了在fpga上用硬體描述語言實現功能模塊的方法，通過功能模塊的硬體化，解決了視頻圖像處理的速度問題。圖像數據的正確採集和顯示輸出是其中的兩個重要的模塊，因此，本文主要完成了圖像數據的採集和顯示輸出的設計。本文設計了採集卡，並要對其工作模式進行了配置和編寫了採集控制模塊，在採集控制模塊的控制下，將數字圖像數據正確無誤的存儲到了sram中。
  8. This paper starts the research of the liquid floated pendulous accelerometer testing system according to the engineering. at first, this paper gives the brief introduction of the history and present status of accelerometer and its testing technology, the working principium and math model of the liquid floated pendu - lous accelerometer, and then, decides the binary width pulse force retrim loop as the design proposal of testing system, researches the transfer function of every part in the system emphasizly, analyses the stability of the whole accelerometer testing system from the angle of control theoretics by the open loop transfer function of system, and designed the correcting net, analyses the basal problems such as resolution, sampling restraint, precision and so on, designs the hardware testing circuits such as preamplification, band - pass filter, alternating amplifier, phase sensitive demodulatorn, pulse - width modulation, frequency scale circuit, moment current generator. finally, using the graphics program language labv - iew which is designed for testing field especially by ni accomplishes the solfware design of testing system, realized the testing functions

    首先對加速度計及其測試技術的發展歷史和現狀，液浮擺式加速度計的工作原理和數學模型等作了簡要的介紹，然後確定了以二元調寬脈沖再平衡測試迴路為設計方案，並從控制理論的角度進行了分析，著重研究了系統中各部分的傳遞函數，利用系統開環傳遞函數分析了系統的穩定性，同時設計了系統的校正網路;分析了二元調寬脈沖再平衡測試迴路的解析度、采樣約束以及測試精度等基本問題，並按照系統分析的結果設計了包括前置放大、帶通濾波、交流放大、相敏解調、脈寬調制、頻標電路以及力矩電流發生器等測試系統各部分硬體電路，驗證了電路的正確性，最後按照測試系統的要求，採用了美國ni公司專為測試領域所開發的虛擬儀器工具? ? labview作為測試軟體開發工具，利用該圖形化編程語言完成了測試系統軟體部分的設計，實現了測試功能。
  9. Thi s dissertation first describes syntax, semanteme and method of modeling hardware of veri1og hdl and vhdl in detai1 so that strong abi1 ity of designing and simu1ating waveform is represented in hardware circuits

    本文首先對兩種硬體描述語言veriloghdl和vhdl在語義、語法及硬體建模方法進行了詳細的描述，說明它們在硬體電路波形表示方面有較強的設計與模擬能力。
  10. At software arrangement, all topper applications are directly based on rock - bottom hardware drive, thus we use clanguage to write application program

    在軟體層次上，所有的上層應用都直接基於底層的硬體驅動，故應用程序以c語言方式編寫。
  11. Bill is titoma s inventor in residence ; he has over 20 years experience doing research for the us military, owns numerous patents and is an expert in electronics and chemistry, especially anything to do with light : blue lasers, uva, uvc, led, optic fiber, liquid light pipes, light boxes, custom light bulbs and leds, power supplies and ballast etc. bill has an extensive network of resources all over asia and the us, and knows how to arrange prototyping and production in such a way that intellectual property doesn t leak out

    其專長為開發無線應用產品軟體與硬體。其撰寫了全世界第一個無線資料傳輸封包，設計了terminal server開發了amps etacs第一款中文手機軟體近端資料轉輸概念，執行過數百個全球的系統，開發過可攜式資料傳輸機，熟稔法律與財務網路系統。其也在德國取得數學學位，精通中文等多國語言。
  12. At last the algorithm of ddmf is achieved by the investigation tool of altera company ? quartus ii and the vhdl language, and its ip core is also achieved which is used not only in the satellite navigation position system, but also in the long pn code dsss system. ddmf investigated in the dissertation gives a good way to design the rapid pn code acquisition in the beidou project, and the technology has the definite theory and practice significance

    此外還應用altera公司的最新的fpga開發工具quartusiiv5 . 1 ，採用了國際標準的硬體描述語言? vhdl語言，對數字差動匹配濾波器和傳統匹配濾波器演算法予以實現，開發了該演算法的軟ip核，可以對所應用的擴頻碼長度， a / d采樣后的數據量化階數，所用擴頻碼等可進行隨意改寫。
  13. After the users input control tasks in three modes : natural language, electric sheet or flow char, the computer will receive the information of control demands by data mining and knowledge discovery. and then illation is leaded to select the hardware and program the software in the inner of the computer. afterward, control program is transformed in the file format of exiting simulation software by using the simulation interface and is opened in the simulation software

    用戶只需在pc機上以自然語言或繪制控制流程圖、填寫表格的方式輸入控制任務，然後在系統內部經過數據挖掘和知識發現分析得到可用控制要求信息，並自動引導推理求解過程進行硬體選型和生成相應的控製程序，最後利用模擬介面，自動將控製程序轉化為現有的控制模擬軟體的文件格式，並在控制模擬軟體中，從而用戶可以對生成的控制系統進行模擬，檢查設計的正確性。
  14. This design for mvbc system adopts top - down eda common design flow. circuit design adopts veriloghdl coding description. function simulation and timing verification adopt simulation tool vcs of synopsys inc, the logic synthesis tool and fpga programming tool adopt the quartus ii of altera inc, and the fpga advice stratix ii ep2s15

    該mvbc系統設計採用業界通用的自上而下的eda設計方法，電路邏輯實現採用veriloghdl硬體語言描述，功能和時序驗證的動態模擬採用synopsys公司的vcs ，而邏輯綜合與fpga實現採用altera公司的集成開發環境quartusii軟體以及stratixiiep2s15的fpga器件。
  15. The second part studies the characteristics of cdma2000 1x reverse link, and implements a softcore design of the cdma20001x rtl soc with hdl ( hardwire desciptionin language ) verilog in accordance with the is - 2000 specifications. the model include the softcore of a spread spectrum modulation and a simple 8 - bit processor. as the same time simulate all the parts of the soc softcore with software modesim

    ，本文的第二部分認真的研究了cdma20001x的反向鏈路的特點，設計反向鏈路的擴頻調製片上系統方案。用硬體語言verilog設計cdma20001x的擴頻調製片上系統的ip軟核。其中包括擴頻調制部分和一個8位的cpu設計。
  16. Physical expression will be limited and stiff, with few arm and hand movements

    肢體語言很拘束，僵硬，手臂和手不怎麼動。
  17. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
  18. The thesis is a research of the pic microcontroller of microchip corporation. the thesis includes a design of a cpu ip core with verilog hdl, and the design bases on up - down design flow

    首先從正向設計和模擬的角度，給pic微控制器中的核心部件-處理器單元建立了一個硬體語言描述的ip模型。
  19. The aim of this paper is to implement the decoder of turbo codes with fpga. the iterative decoding algorithms and how to implement them with hardware language have been discussed in the paper

    本文以turbo碼譯碼器的fpga實現為目標，對turbo碼的迭代譯碼演算法及用硬體語言實現其譯碼演算法進行了深入研究。
  20. We choose the max _ log _ map decoding algorithm and use the technology of altera and its cyclone2 devices as the fpga design scheme according to all the factors. taking advantage of the technology of fpga, the means, called “ top - down ” and “ down - top ”, is applied in the design of fpga in this paper

    在綜合考慮設計方案的綜合性能、復雜程度、系統規模、系統延時和成本等各項因素后，本次設計選擇了altera公司的cyclone2器件來完成turbo碼譯碼演算法（ max _ log _ map ）在硬體語言上的模擬設計。
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