積分電路的英文怎麼說

中文拼音 [fēndiàn]
積分電路英文
circuit, integration

  • : Ⅰ動詞(積累) amass; store up; accumulate Ⅱ形容詞(長時間積累下來的) long standing; long pending...
  • : 分Ⅰ名詞1. (成分) component 2. (職責和權利的限度) what is within one's duty or rights Ⅱ同 「份」Ⅲ動詞[書面語] (料想) judge
  • : Ⅰ名詞1 (有電荷存在和電荷變化的現象) electricity 2 (電報) telegram; cable Ⅱ動詞1 (觸電) give...
  • : 1 (道路) road; way; path 2 (路程) journey; distance 3 (途徑; 門路) way; means 4 (條理) se...
  • 積分: 1. [數學] integral; integrate; integration 2. [體育] (積累的分數) accumulate points
  • 電路: [訊] circuit (ckt); electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...

※中文詞彙積分電路在字典百科國語字典中的解釋。

  1. We have designed the scanning and control system, which includes a pre - amplifier, a pid feedback and scanning - control circuit, high - voltage amplifiers and so on. the function of controlling scan and feedback has been realized

    設計完成包含有前置放大、 pid反饋和掃描控制、高壓放大等掃描控制在內的掃描控制系統,完成各部性能的測試及功能調試,實現反饋和掃描控制。
  2. Type plane wave incidence and the input admittance of cylindrical monopole antenna, it is testified that the proposed method is more accurate than the conventional square contour integration method

    型平面波的散射流以及單極細圓柱形天線的輸入導納,對所提出的方法作了驗證,證明了該方法比常用的矩形法對細導線上流的模擬要精確得多。
  3. Circuit design is the basis of design of demultiplexer. speed, power and chip area are the main factors that should be considered in circuit design. every circuit structure has its merits and drawbacks, e. g. cmos logic family has a slower speed, but lower power, smaller area, scfl ( source couple fet logic ) family has a higher speed, but higher power, larger area. we should choose a proper circuit structure or their mixed structure for certain design to get a good tradeoff among the three factors. flip - flop is the fundamental element of demultiplexer, setup time and hold up time are key factors, which influence the speed of circuit, thus the design aim is how to reduce them. in this thesis we place emphasis on the design of scfl latches

    速度、功耗、面設計要考慮的主要因素,不同的形式具有不同的優缺點,如cmos互補邏輯功耗低,面小,速度相對較慢; scfl (源極耦合fet邏輯)速度高,功耗和面較大。所以要針對具體設計需要選用適當的形式或其組合結構,以滿足設計要求。觸發器是接器的基本組成單元,建立時間和保持時間是影響速度的關鍵,所以減小建立時間和保持時間是觸發器設計的主要目標,本文著重介紹了scfl鎖存器的設計和優化方法。
  4. Cls21 - i metallized polypropylene capacitors have low dissipation factor, stable capacitance, puny thermoguotiety. they can steadily work on logic control circuits & integral circuits and phase etc of instruments

    型金屬化聚碳酸酯容器損耗小,容量穩定,溫度系數小,能穩定地工作在精密儀器、儀表的邏輯控制積分電路等場合。
  5. By careful selection of the ratio between this resistor and the integrating resistor ( a few tens of ohms in the recommended circuit ), the comparator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. 3

    通過小心選擇這個阻和阻之間的比值(在推薦線里,大約是數十歐姆) ,比較器的延遲就可能被補償,最大的時鐘頻率可近似延伸到3 . 3倍。
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