系統虛地址 的英文怎麼說

中文拼音 [tǒngdezhǐ]
系統虛地址 英文
system virtual address
  • : 系動詞(打結; 扣) tie; fasten; do up; button up
  • : Ⅰ名詞1 (事物間連續的關系) interconnected system 2 (衣服等的筒狀部分) any tube shaped part of ...
  • : Ⅰ名詞1 (空虛) void; emptiness 2 (政治思想等方面的道理) guiding principles; theory 3 (二十八...
  • : 名詞(建築物的位置; 地基) location; site; ground; foundation
  • 系統 : 1. (按一定關系組成的同類事物) system 2. (有條理的;有系統的) systematic
  1. Security, too, is a key issue for switching the traditional private nforork to vpn. security of mpls wn architectur is analyzed thorouguy in this thesis, including septheion of address space and route, hiding of the mpls core smicture, resistance of attacks, impossibi1ity of 1abe1 spoofing

    安全性是擬專用網能否取代傳專用網的關鍵,本文對mplsvpn體結構的安全性進行了深入分析,包括空間和路由的隔離、隱藏mpls核心結構、抵抗攻擊、抵抗標記欺騙等,從而得出mplsvpn與atm framerelay具有相同安全級別的結論。
  2. In this thesis, first, we present the theory of sess system, the generation of the sess spreading code and its characteristics and the acquisition theory of conventional spread spectrum communication system. an efficient acquisition scheme based on periodically transmitting the synchronization head, which is composed of binary chaotic codes, using the matched filter and automatic decision threshold - level control based on a so - called constant false alarm criterion for sess system is present. the acquisition model of sess system is built and simulated in the awgn channel, the raleigh fading channel and imulti - address interfere condition

    本文首先概述了自編碼擴頻通信的原理、自編碼擴頻序列的產生方法及其特性和擴頻通信編碼同步的理論,然後針對自編碼擴頻通信提出了擴頻序列捕獲方案:周期性加入混沌序列同步碼,並採用恆警率匹配濾波器捕獲法;在加性白高斯噪聲通道、瑞利衰落通道和多干擾情況下進行了模擬,分析了各種捕獲性能:在選擇性能最優的混沌序列、適當的序列長度、警概率及門限值的情況下,可以獲得較短的捕獲時間和較大的捕獲概率。
  3. In a virtual - memory system, programs are given access to a larger set of addresses than is physically available, and a dedicated memory manager maps these logical addresses to actual locations, using temporary storage on disc to hold the overflow

    擬內存中,程序可以訪問超出可用物理內存的更大的集合,專用內存管理程序將這些邏輯映射到實際,使用磁盤上的臨時存儲保存超出的部分。
  4. Now the emphasis is transferred to the design and implementation of memory system. before a deep discussing, some basic knowledge is introduced, such as the memory classification and hierarchy, address space, access controlling, cache, memory coherence, and the popular memory system implementation method. then the archteture of the target memory system is presented and divided into two subsystems, the virtual memory management subsystem and memory access subsystem, according to their function

    接下來本文將重點轉移到研究已定目標vliw處理器存儲的設計和實現,先對存儲設計涉及的存儲器及其組織層次、空間、訪問控制、 cache 、存儲一致性、常見的實現方式等因素作了分析,然後給出了目標存儲的總體框架,並按功能將其劃分為存管理和訪存兩個子
  5. In the following virtual memory management subsystem design, after analyzing the hardware - software dividing line and cooperation in detail, four key issues of virtual memory manage subsystem design are discussed : the classification of processor operating mode, the partition of virtual space, the access controlling and the design of control coprocessor ( ccop ). a virtual manage subsystem prototype is then presented

    存管理子設計的討論中,詳細分析了存管理中軟硬體的分工協作,深入研究並解決了存管理子設計的四個核心問題:處理器工作模式分類、空間劃分、訪問控制和控制協處理器設計,並在此基礎上給出了一個存管理子原型。
  6. Awe extends the capabilities of applications running on 32 - bit operating systems by allowing access to available physical memory in excess of the limits set on their configured virtual memory address space

    通過允許訪問超過在所配置擬內存空間上設置的限制的可用物理內存, awe可擴展32位操作上運行的應用程序的功能。
  7. In the memory access subsystem design, on the basis of deeply discussing three kernel problems encountered in cache design, this paper presents a li cache model with virtual index and physical tag, using a hardware - based method to solve the synonym problem, and adopting l2 cache " s initiative requesting for the li cache " s snoop service to keep the consistency between li cache and l2 cache, then takes li data cache as an example to illustrate the li cache implementation

    在訪存子的設計中,深入研究並解決了cache設計中的三個核心問題:採用索引、實tag ,用硬體方式解決synonym問題,以l2cache向l1cache主動請求snoop服務的方式實現兩級cache間的一致性。在此基礎上,給出了一個l1d - cache原型。
  8. In order to solve the problems about unfixed instruction length, stack - orientation and addressing virtualization in jvm instruction set, the instruction fetch unit, stack cache and mechanism of address translation in java chip system are studied

    為了解決java擬機指令中指令不定長、面向堆棧和擬化等問題,本文研究了java晶元中取指部件、堆棧緩沖部件和轉換機制以及相應物理存儲器的管理等關鍵技術。
  9. In a virtual storage system, a fixed - length block that has a virtual address and that is transferred as a unit between real storage and auxiliary storage

    擬存儲(器)中,具有一個並且可以在實存儲器和輔助存儲器之間作為一個單位來傳送的一種長度固定的(數據)塊。
  10. That field of the total address ( virtual or physical ) that defines the page containing the desired address in apaged memory system

    在分頁存儲器中,或實總中定義包含所需的頁面的欄位(中的內容) 。
  11. A block of instructions, or data, or both, that can be located in main storage or in auxiliary storage. segmentation and loading of these blocks is automatically controlled by a computer

    擬存儲(器)中,具有一個並且可以在實存儲器和輔助存儲器之間作為一個單位來傳送的一種長度固定的(數據)塊。
  12. If there is more than 16 gb of physical memory available on a computer, the operating system requires 2 gb of virtual address space for system purposes and therefore can support only a 2 gb user mode virtual address space

    如果計算機上的可用物理內存超過16 gb ,操作就需要2 gb的擬內存空間供使用,因此只能支持2 gb的用戶模式空間。
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