組合邏輯 的英文怎麼說

中文拼音 [zǔgěluó]
組合邏輯 英文
combination logic
  • 組 : Ⅰ名詞1 （由不多的人員組成的單位） group 2 （姓氏） a surname Ⅱ動詞（組織） organize; form Ⅲ量詞（...
  • 合 : 合量詞（容量單位） ge, a unit of dry measure for grain （=1 decilitre）
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 組合 : 1 （組織成為整體） make up; compose; constitute 2 （組織起來的整體） association; combination3 [...
  • 邏輯 : logic
  1. Combination logic function

    組合邏輯功能
  2. It can give bdd presentation of boolean function or arbitrary combination logic circuits which are presented by cdl, and can realize different operation of boolean function by the operation to bdd

    能完成對任意基於cdl語言描述的組合邏輯電路或布爾函數，實現其bdd表示並通過對bdd的操作實現對相應組合電路或布爾函數的操作。
  3. In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework

    另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。
  4. The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance

    模擬實驗結果證明了改進演化演算法對于實現函數級數字組合邏輯電路的硬體演化是可行的，並且提高了演化演算法的演化效率和收斂性能。
  5. Evolvable algorithms are applied to functional digital combinational logic circuits with the structure of classicepglo chip of altera co. and the detailed analyses of typical examples are also given

    結合altera公司classicep610晶元的結構，研究了將演化演算法應用於函數級數字組合邏輯電路的硬體演化，並且對典型實例進行了詳細分析。
  6. Complex programmable logic device ( cpld ), usually used to develop asic, is widely used in digital system to accomplish complex combinational and sequential logic

    復雜的可編程邏輯器件（ cpld ）廣泛地用於數字系統中，常用作設計自己的專用集成電路，可實現復雜的組合邏輯和時序邏輯。
  7. Digital circuit includes two kinds - the assembly logic circuit and the sequential logical circuit, the characteristic of the assembly logic circuit is that the output signal is only the function which enters the signal and has nothing to do with the entering state at any other moment, it has no function of memory

    摘要數字電路分為組合邏輯電路和時序邏輯電路兩類，組合邏輯電路的特點是輸出信號只是該時的輸入信號的函數，與別時刻的輸入狀態無關，它是無記憶功能的。
  8. This paper focuses on the combitional logic synthesis including two level logic synthesis and multiple level synthesis. and it is a part of control flow synthesis in a controller synthesis system. in this paper following problems are proposed and implemented : ( 1 ) implement the algorithm " espresso ", and make it suit to the system

    本文所完成的組合邏輯綜合的研究與實現是控制流綜合系統的一個組成部分，其中包括： （ 1 ）引入並實現了兩級邏輯綜合的「 espresso 」演算法，定義與系統相適應的數據結構，重新測試各種開關條件，使之適用於系統的實際應用。
  9. Functions of logic synthesis are to transform and optimize the combinational logic functions and produce the pure logic level structural description

    邏輯綜合的功能是對組合邏輯函數的描述進行轉換和優化，生成與邏輯功能描述等價的優化的邏輯級純結構描述。
  10. Digital design ： binary system, boolean algebra, logic gates, simplification of boolean functions, combinational logic. analog design ： amplifiers, frequency response, feedback, operational amplifier

    數位設計：二進位制、布氏代數、邏輯閘、布氏函數的化簡、組合邏輯電路。類比設計：放大器、頻率響應、反饋系統、運算放大器。
  11. Design basis of combinational logic circuit

    組合邏輯電路設計基礎
  12. Then studis on new models and new approaches based on boolean process in delay automation are made. analytical delay model is improved with the new concept of sensitization, based on which delay matrix is proposed to describe the delay of circuit modules. then introducing hierarchical delay analysis methods into delay matrix analysis, a novel exact hierarchical delay ananlysis method is presented

    在組合邏輯電路精確定時方面，本文用波形多項式偏導定義的敏化概念改進了解析延時模型，在此基礎上建立了基於敏化的延時矩陣以描述電路模塊的延時，隨后將層次化延時分析方法引入基於延時矩陣的延時分析中，形成一種新的精確的通用電路層次化延時分析方法。
  13. Digital combined logic circuit modeling and simulation based on matlab

    的數字組合邏輯電路建模與模擬
  14. A combinational logic element having at least one input channel

    一種至少有一個輸入通道的組合邏輯元件。
  15. Combinational logic element

    組合邏輯元件
  16. For examp1e, the sort arithmetic so1ves 1eve1 partition of combination 1ogic ; the computing input waveform of sensitized path makes the possib1e of conf1rm the minimum c1ock circ1e ; the cyc1e - - based method for synchronous op tajg1fyjct7 : @ + $ { 4it x sequentia1 circuits improve the speed of waveform simu1at ion

    其中，編排級數法確定了組合邏輯的層次關系；通路敏化輸入波形方法決定了最小時鐘周期；基於周期的同步時序電路的模擬演算法加快了模擬的速度等。
  17. An algorithm of combinatory logic optimization based on rough set

    基於粗糙集的組合邏輯優化演算法
  18. Finally, the effect of the diffraction aperture is studied during the course of reducing the scale of the diffraction aperture to the limit of the scalar diffraction theory

    基於仙農（ shanon ）的組合邏輯設計理論，用光學矢量-矩陣乘法器對超前進位加法器模型的光學實現進行了數值模擬。
  19. Combinational logic circuit

    組合邏輯電路
  20. Analysis of competition and adventure in assembled - logic circuits using pspice simulation

    分析組合邏輯電路中的競爭冒險
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