結果寄存器 的英文怎麼說

中文拼音 [jiēguǒjìcúnqì]
結果寄存器 英文
result register
  • 結 : 結動詞（長出果實或種子） bear （fruit）; form （seed）
  • 果 : Ⅰ名詞1 （果子） fruit 2 （事情的結局; 結果） result ; consequence 3 （姓氏） a surname Ⅱ動詞（吃...
  • 存 : 動詞1 （存在; 生存） exist; live; survive 2 （儲存; 保存） store; keep 3 （蓄積; 聚集） accumulat...
  • 器 : 名詞1. （器具） implement; utensil; ware 2. （器官） organ 3. （度量; 才能） capacity; talent 4. （姓氏） a surname
  • 結果 : 結果bear fruit; fruit
  1. The floating - point status and control register fpscr captures status and exceptions resulting from floating - point operations, and the fpscr also provides control bits for enabling specific exception types, as well as for selecting one of the four rounding modes

    浮點狀態和控制寄存器（ fpscr ）捕獲浮點操作的狀態和異常結果， fpscr還具有控制位，以支持特定的異常類型和對四種舍入模式之一的選擇。
  2. Focusing on a 64 - bit high - performance general purpose microprocessor with fully independent intellectual property, the thesis investigates a 128 - word 65 - bit general register file with 12 - read and 8 - write ports which is a representational one for its large - scale and multi - port characteristics in that microprocessor, and realizes its full custom design with high speed in read and write access. from the layout simulation result, under the 0. 18um process, the upper limit working frequency for the register file is 900mhz

    本文面向一款具有完全自主知識產權的64位高性能通用處理器，對其中具有代表性的128字65位12讀埠和8寫埠的通用寄存器文件進行研究，實現了它的高速讀寫全定製設計，版圖模擬結果表明，在0 . 18um工藝下，設計可以工作的時鐘頻率上限為900mhz 。
  3. These results are then committed to a separate architectural register file during in - order retirement

    這些結果然後在有序退回時，存放在一個獨立的結構寄存器文件中。
  4. Some computers have several fast registers which can be used to hold temporary results.

    某些計算機有若干快速寄存器，它們能用來保存中間結果。
  5. The result shows that the soft and hard faults will have different significance to the performance of circuits at a wide range of defect size. the relationship between yield and reliability is concerned for a long time

    最後以一個4x4的移位寄存器為例，驗證了該方法的有效性，最後的模擬結果給出了在不同粒徑時，軟、硬故障對電路性能影響程度的比較。
  6. The control logic is completed by fpga. the system control software provides several control functions of pci and dsp, such as adjusting pci bus configure registers, setting work mode, downloading dsp programs and data, reading processing results from dsp and saving data

    系統控制軟體提供了pci和dsp的控制功能：修改pci總線的配置寄存器、設置工作方式、向各個dsp下載用戶程序與數據、從dsp中讀取處理結果、數據存檔等操作。
  7. A raw ( read after write ) dependency loop model is developed in this paper to analyze the raw hazards of register operands in complex pipeline. based on this model, a " dynamic " data forwarding policy is suggested to reduce the pipeline stalls caused by data raw hazards. theoretical analysis and practical experiments both show that the average cpi increment caused by data raw hazards can be reduced effectively by the dynamic data forwarding strategy

    對于單發射結構的處理器，降低cpi值的根本途徑在於通過各種軟硬體技術減少流水線的停頓，本文構造了一個raw相關環路模型用於分析流水線中寄存器操作數的raw競爭現象，並提出了一種「動態」數據旁路優化策略，可以最大程度地減少復雜流水線中因數據的raw競爭而導致的互鎖停頓，理論分析和實測結果充分表明「動態」數據旁路機構可以有效地降低流水線因raw互鎖導致的平均cpi增量。
  8. In the dissertation, we discuss the issues on loop unrolling, register allocation, and cost model, etc. some of the achievements are applied to the implementation of an open source compiler

    本文結合epic體系結構特性，對軟體流水技術中的循環展開、寄存器分配、開銷模型和決策框架等領域進行了研究，並將其中一些成果應於一個開放源碼的編譯器，取得了比較好的效果。
  9. This supports a 40 - entry physical register file that holds temporary write - back results that can complete out of order

    此支持40種物理寄存器文件，此文件含有能混序完成的臨時回寫結果。
  10. By default, the compiler uses the coprocessor s 80 - bit registers to hold the intermediate results of floating - point calculations

    默認情況下，編譯器使用協處理器的80位寄存器保存浮點計算的中間結果。
  11. With software and hardware co - design method, this paper proposes an algorithm to calculate register lifetime in programs, and the control of writing results back into rf is implemented through an enable control signal provided by instruction encoding at compile time

    基於軟硬體協同設計的思想，在研究局部變量生存期演算法的基礎上，本文提出了通過編譯器指令編碼實現對硬體結構的使能控制，即控制流水輸出結果是否寫回寄存器文件，以減少對寄存器文件的寫次數，從而降低寄存器文件埠的讀寫壓力。
  12. Calculation for the data from simulation shows that power dissipation of det shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart set shift register

    對模擬所得數據的計算結果表明，與實現相同功能的單邊沿移位寄存器相比，由於工作頻率減半，雙邊沿移位寄存器的功耗有明顯降低。
  13. Calculation for the data resulted from simulation shows that power dissipation of det shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart set shift register

    對模擬所得數據的計算結果表明，與實現相同功能的單邊沿移位寄存器相比，由於工作頻率減半，雙邊沿移位寄存器的功耗有明顯降低。
  14. Selects the destination register for the result of the current stage identified by

    標識的當前貼圖層的結果選擇目標寄存器。
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