網表 的英文怎麼說

中文拼音 [wǎngbiǎo]
網表 英文
net list
  • 網 : Ⅰ名詞1 （捕魚捉鳥的器具） net 2 （像網的東西） thing which looks like a net 3 （像網一樣的組織或...
  • 表 : Ⅰ名詞1 （外面;外表） outside; surface; external 2 （中表親戚） the relationship between the child...
  1. Instead, the seven television network said hawkins visited dibley ' s bathurst high school on tuesday for a private lunch date with daniel, and to speak to the school assembly, where she apologized for all the fuss

    然而，據seven電視網表示，霍金斯已於周二參觀了迪布利就讀的巴塞斯特高中，並與迪布利悄悄進行了午餐約會。
  2. Multi - level plain weave surface filtration structure, good effects in countercurrent rinsing

    多層平織絲網表層過濾結構，逆流清洗效果好，清洗簡單。
  3. Vatican foresees excommunication of two chinese bishops the vatican says it expects to excommunicate two men who were ordained as catholic bishops in china this week without the approval of pope benedict

    梵蒂網表示將革除兩名本星期在未經教皇本篤十六世批準的情況下在中國祝聖的天主教主教的教籍。
  4. Rdf is a language for presenting information to the world wide web

    Rdf是用於向萬維網表達信息的語言。
  5. The design of this chip sticks to the general methodology of hdl design. lt is entered in hdl format with innoveda ' s visual hdl and simulated with modelsim simulator, after synthesized with fpga compiler ii, the edif is entered in quartus ii, which is supplied by altera corporation to place and route. the sdo file produced by quartus ii is backannotated to the netlists and timing - simulation is been done. the success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with hdl

    在innoveda的visualhdl設計平臺上用hdl語言完成了設計輸入，使用modelsim模擬器完成了功能模擬，使用synopsys的fpgacompiler進行了基於alterafpga庫的網表綜合，最後將edif網表輸入altera的布局布線工具quartus中進行了布局布線，將生成的sdo文件反標到modelsim模擬器中進行了時序模擬，該設計的成功，再一次表明了hdl設計方法的正確性和有效性。
  6. Fill in the “ internet product login application form ” with legal person sign and stamp

    填寫附件中的進網表，要求法人簽字蓋章（兩頁）
  7. Yet there was apparently only one spy-houghton-serviced by the whole lonsdale/kroger apparatus.

    然而，整個朗斯代爾克羅格間諜網表面上只經營一個間諜--霍頓。
  8. According to the hardware structure of the main experiment board, the circuit netlist transformation program translates the visual circuit description to the actual netlist

    根據實驗主板的硬體結構，設計的專用電路網表轉化程序，將便於用戶理解的圖形化的電路描述轉化為便於實際硬體操作的電路網表。
  9. Its surface is often covered with ribosomes, forming rough er

    內質網表面常結合有核糖體，被稱為糙面內質網。
  10. For above problems, i design boole process - based algorithm. for example, hazards finding theory work out a formal method of finding hazards by waveforms computing ; waveforms increasing algorithm settle the defect of boole process in feedback cycle treatment ; false paths discerning algorithm can delete useless nodes in netlist effectively ; inertia conflict eliminating method describes the state of nodes truelier and reduces computing

    其中，冒險檢測定理給出了通過波形運算檢測電路中冒險現象的哈爾濱工程大學碩士學位論文形式化方法;波形遞增演算法解決了boole過程在處理電路中反饋環問題上的缺陷;偽路徑識別演算法能夠有效地去除電路網表中的無用節點;而慣性沖突消除法能使對節點狀態的描述更加真實，並減少了計算量。
  11. It presents the verification strategy used in the whole eda design flow of the chip. the simulation on module level ( inc. post - layout ) uses the software event - driven simulator, the simulation of the associated modules or whole system uses cycle - based simulator and hardware emulator, for the gate - level netlist produced by using top - down design flow, the sta tool can analyze the static timing, and more formal verification is used to ensure the correct function

    本章還提出了系統在整個eda設計流程中的設計驗證策略方法：模塊級的模擬（包括布線后的模擬）全部採用事件驅動式的軟體模擬工具來驗證，各大模塊的聯合模擬及整個晶元的功能驗證（寄存器傳輸級與門級）使用基於周期的模擬工具和硬體模擬器；對于採用top - down的設計方法得到的門級網表使用專門的靜態時序分析工具來進行時序分析以及採用形式驗證來保證正確的功能。
  12. It induces logic and delay to waveform, and describes the continuous states of nodes in netlist by waveform. it can realize simulating continuous states for integrated circuits by computing waveforms

    它把邏輯和延遲有機地結合起來歸納為波形，並用波形來描述電路網表中節點的連續時間狀態，通過對波形的計算實現整個電路的連續時間狀態模擬。
  13. But circuitry net table which is synthesized by synthesizer is not necessarily achieve the demand of designer, so aim for the speed demand of destination, the sequence circuit which is synthesized demand speed optimization

    但是由於綜合器綜合得到的電路網表不一定能達到設計者的設計要求，所以需針對給定的速度要求，對綜合得到的時序電路進行速度優化。
  14. Simulation of digital circuits is based on computing of logic and delay for component in circuit netlist, so for obtaining correct simulation result, i must have logic computing correctly and delay analysis accuracily

    由於數字電路的模擬是基於對電路網表中的元件進行邏輯和延時計算的，所以要想得到正確的模擬結果，必須進行正確的邏輯運算和準確的延時分析。
  15. Recurring to the circuit netlist, the mcu of the main board finishes the digital setting for the parameters and the structure of the experiment circuit, which realize to do all kinds of electronics experiments in the same main experiment board

    控制實驗主板的單片機藉助于電路網表所提供的信息，完成實驗電路結構和參數的全數字化設置，從而實現了在同一實驗主板上完成不同的電工電子實驗。
  16. Results show that the empty and porous balls of tio2 were grown on the surface of fine tourmaline particles dispersing in the tio2 film based on the copper net, under the effect of the nature electric field of fine tourmaline particles

    用溶膠?凝膠技術在紫銅網表面成功生長電氣石tio _ 2復合薄膜，該復合膜中電氣石微粒表面形成了tio _ 2空心球簇結構和tio _ 2層狀微粒簇結構。
  17. The project of developing the core comes from a national key program in science and technologies, study on mcu high level language description and embeded system technology. the project is followed the top - down design way

    這個項目遵循了自上而下的設計流程，從系統劃分、編寫代碼、 rtl模擬、綜合、門級模擬，到布局布線、電氣規則檢查、設計規則檢查，網表比較等。
  18. Furthermore, timing simulation and static - state timing analysis were made. by doing these, netlist files were got

    並進一步做時序模擬和靜態時序分析，產生輸出網表文件，最後下載到fpga進行系統實現。
  19. Then describes the 4 function modules in vhdl, the vhdl programs have passed compile and debug in maxplus ii, the results of function simulation and timing simulation all prove that the design is correct, at last, maxplus ii generates a netlist file which can be download into chip

    然後使用vhdl硬體描述語言對四大功能模塊進行描述，在maxplus環境下編譯、調試通過，功能模擬和時序模擬結果證明設計正確，最後生成可下載的網表文件。
  20. The police thanked the taxi industry for the full operation and support in providing information which led to arrest of the taxi robbery suspects

    警方對于的士同業的通力合作與支持，就有關劫案提供資料以致疑匪落網表示致謝。
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