線程級并行 的英文怎麼說

中文拼音 [xiànchéngjíbīngháng]
線程級并行 英文
tlp（thread level parallelism
  • 線 : 名詞1 （用絲、棉、金屬等製成的細長的東西） thread; string; wire 2 [數學] （一個點任意移動所構成的...
  • 程 : 名詞1 （規章; 法式） rule; regulation 2 （進度; 程序） order; procedure 3 （路途; 一段路） journe...
  • 級 : Ⅰ名詞1 （等級） level; rank; grade 2 （年級） any of the yearly divisions of a school course; gra...
  • 行 : 行Ⅰ名詞1 （行列） line; row 2 （排行） seniority among brothers and sisters:你行幾? 我行三。where...
  1. Tlp thread - level parallelism

    線程級并行
  2. The appearance of tlp greatly improves the performance and throughput of the processors

    線程級并行性的開發大大提高了處理器的性能和處理能力。
  3. In chapter 4 we discuss the design of the high speed and high performance vlsi and its imp1ementation, firstly we ana1yze and compare the features and ru1es of al1 kinds of fft algorithm, adopt complex radix 4 butterfly calcu1ation as basic alu, then discuss all kinds of process architectures, the design thoughts, rule, method, technique way, the characteristics of the design are r4 dit algorithm, pingpong ram design method and pipeline structure between stages. we also analyze the limited word length effect and the method to avoid overflow of the fixed points fft process, bring out the expandable platform mode

    第四章主要討論了高速高性能的快速傅立葉變換處理器的設計和實現，首先分析和比較了各種快速傅立葉變換演算法的特性和規律，提出基4蝶算的演算法具有最好的性價比，討論了順序、級聯、并行和陣列的處理結構，闡述了設計高速高性能快速傅立葉變換處理器時的設計原則、設計思路、所採用的技術路線，驗證並測試fft處理器，分析了定點fft處理過程由於有限字長效應所產生的量化誤差的范圍及防溢出控制辦法，提出了可擴展平臺模式。
  4. ( 4 ) we make further improvement in fox algorithm on processors organized as a rectangular grid, and we also develop multi - level parallelisms and make performance optimization for this improved algorithm on smp cluster at process level, thread level and instruction level

    （ 4 ）對長方網格上的并行矩陣乘演算法做了進一步改進，並針對改進演算法，分別從進程級、線程級和指令級對其進行多級并行性開發與性能優化。
  5. With such research background, this dissertation focuses on the research of hardware techniques for thread level parallelism in high performance microprocessors, especially the multithreaded microprocessor which has superscalar execution core

    在這種背景下，本文研究支持線程級并行的硬體技術，尤其是執行單元為超標量結構的多線程處理器。
  6. The microprocessor architecture design has entered the era of thread level parallelism

    目前微處理器系統結構設計已經進入線程級并行的時代。
  7. Based on the dlx simulator, smarcof is modified with sma specific extension and heuristic optimizing rules. simulation of spec code shows that above rules could exploit hybrid parallelism effectively with rather low overhead

    基於spec代碼的模擬表明該方式能夠有效的挖掘系統的潛力，實現深度的指令級并行和線程級并行開發。
  8. Multithreaded microprocessor, which has many hardware contexts sharing an execution core, can efficiently exploit both the instruction level parallelism and thread level parallelism to acquire higher performance and better performance / power ratio

    多份硬體現場共享一組執行單元的多線程處理器能靈活地利用程序中的指令級并行和線程級并行，從而提供更好的性能。
  9. Also discussed the methods on how to realize the cwt both in time - domain and frequency - domain and how to design the gm - c bandpass filter used in realization of cwt. in order to optimize the performance of gm - c filter, linearization techniques are investigated and proposed. due to process variation and parasitics, an automatic tuning is designed for center frequency / 0 and quality factor q also, in this thesis, 16 - channel analogue cmos cwt circuit has been realized

    論文圍繞連續小波變換的模擬電路實現這一熱點問題，討論了連續小波變換的時域和頻域實現方法；具體分析了并行結構與串列結構的優缺點；研究了頻域法中的跨導-電容帶通濾波器的設計；給出了改善跨導輸入級傳輸特性的線性程度並擴大線性范圍的具體方法；設計了片內自校正（可調諧）環節使濾波器參數自動調整到設計標準值；最後給出了16通道濾波器組實現小波變換的方法。
  10. Consider a machine control system that needs to control a linear stage, rotate multiple shafts, control lighting and read in video data ; in a system like this, there are multiple processes that must happen deterministically, in real - time, and in parallel

    考慮到一個機器控制系統需要控制一個線性電路級，旋轉多個軸，控制照明和視頻數據的讀取，因此，在這樣一個系統中，同時有多個進程必須獨立、實時、并行發生。
  11. Among them, openmp, which brings competitive performance as lightweight processes, is considered as a better choice than posix threads and mpi

    分析結果認為，使用openmp實現的并行程序，在性能上與使用輕量級進程的實現相當，優于使用posix線程和mpi的實現。
  12. Also, the relactions between the best block size for matrix transpose and the size and associativity of the processor ' s cache is formulized. for parallel optimization, several programming models available on a numa system, such as lightweight processes ( sproc ), posix threads, openmp and mpi, are compared, and their speedup and coding complexity are analyzed

    對于sar成像處理的并行優化，本文對比了在numa架構上可用的幾種并行編程模型：輕量級進程、 posix線程、 openmp和mpi ，針對numa架構和sar成像處理的特點從加速比、編程復雜度等多個方面進行了討論。
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