編程邏輯陣列 的英文怎麼說

中文拼音 [biānchéngluózhènliè]
編程邏輯陣列 英文
programmed logic array
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 程 : 名詞1 （規章; 法式） rule; regulation 2 （進度; 程序） order; procedure 3 （路途; 一段路） journe...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 陣 : Ⅰ名詞1 （作戰隊伍的行列或組合方式） battle array [formation]: 布陣 deploy the troops in battle fo...
  • 列 : Ⅰ動1 （排列） arrange; form a line; line up 2 （安排到某類事物之中） list; enter in a list Ⅱ名詞1...
  • 編程 : c programming
  • 邏輯 : logic
  • 陣列 : [統計學] array陣列處理機 array processor; 陣列印表機 array printer; 陣列雷達 [電學] array radar
  1. In the third part, gives a new fft algorithm for realization ofdm modulation in fpga

    第三部分為在的現場可編程邏輯門陣列（ fpga ）上實現ofdm調制模塊。
  2. With the quickly development of field programmable gate array, fpga with more than million logic gates has been used

    隨著fpga （現場可編程門陣列）技術的快速發展，萬門以上乃至幾十萬門邏輯陣列的使用越來越普遍。
  3. The system uses the permanent magnet synchronous machine as the driver motor based on the idea of polygonal flux linkage locus and the permanent magnet brush - less motor is as the momentum balance motor by means of speed and current loop in order to track driver motor precisely and rapidly. the harmonious control of driver motor and balance motor is realized by making full use of the dsp hardware resource and complicated programmable logic device. the software design is composed of c and assembly language to realize motor control arithmetic of polygonal flux linkage locus

    衛星天線伺服控制系統以正弦波永磁同步電機作為驅動電機，採用多邊形磁鏈軌跡法（電壓空間矢量法）的控制策略；動量平衡電機採用永磁無刷直流電機，通過電流環、速度環達到快速、精確跟蹤驅動電機的目的，確保了衛星姿態恆定；設計方案中充分利用了dsp硬體資源和復雜邏輯陣列實現了驅動電機和平衡電機的協調控制，並通過c語言和匯編語言的混合編程實現了電機的多邊形磁鏈軌跡控制演算法。
  4. A magnetic processor constitutes an array of logic gates, each of them programmable individually by the software

    磁處理器由邏輯閘陣列所組成，其中每個閘都可以由軟體獨立編程。
  5. Pld refer to the programmable logic device. it is a kind of chip that can be written the design of integrated circuits into its logic arrays

    Pld是指可編程邏輯器件，是一種可將集成電路的設計用編程的方式寫入到其邏輯陣列結構中的一種晶元。
  6. Programmable logic array

    可編程序邏輯陣列
  7. Researched the methods to test configrable logic block ( clb ) and its sub - blocks. based on a “ divide and conquer ” methodology, the clb resources are divided into three basic blocks : logic units, carry logic module ( clm ) and lut ’ s ( look up tables ) ram - mode. the testing configurations are implemented based on a two - dimensional array structure for logic blocks

    主要基於「分治法」對clb及其子模塊進位邏輯（ clm ） 、查找表（ lut ）的ram工作模式等進行了測試劃分，分別實現了以「一維陣列」為基礎的測試配置和測試向量，以較少了測試編程次數完成了所有clb資源的測試。
  8. Pla specification for harmonized system of quality assessment for electronic components - blank detail specification : programmable logic arrays

    電子元器件用質量評估協調體系規范.空白詳細規范:可編程序的邏輯陣列
  9. This course consists of lectures and labs on digital logic, flipflops, pals, counters, timing, synchronization, finite - state machines, and microprogrammed systems

    本課包括了數字邏輯、觸發器、 pal （可編程邏輯陣列） 、計數器、時序、同步、有限狀態機、和微控制系統方面的講課與實驗。
  10. To realize the real - time tracking image target, we use the cpld ( c ' omplex programmable logic device ) to control the system logic and use ipga ( field programmable gate array ) to preprocessing the image

    為了滿足系統的實時性要求，運用大規模可編程邏輯陣列cpld進行邏輯控制和現場可編程門陣列fpga對採集的視頻圖像做預處理。
  11. And then, aiming at the deficiency of conventional design, the high - compositive fpga ( filed programmable gate array ) chip is used as the core in this project to deal with the signal of six encoders in real time

    其次針對以往設計的不足，採用了以高度集成的fpga （現場可編程邏輯陣列）晶元為核心的設計方式，實現六路光電編碼器信號的同步實時處理。
  12. Pal : programmable array logic

    可編程陣列邏輯
  13. With the reconfigurable computing systems, the time of convolution processing is reduced to a fortieth of the computing on common pc versus without of it

    X86可重構計算系統由通用處理器和現場可編程陣列邏輯組成，該系統應當稱為混合系統。
  14. In order to resolve the contradiction between real - time and arithmetic complex in the television tracking capture system, the paper designs the real - time target track processing system which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor, the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image

    摘要為解決電視捕獲跟蹤瞄準系統中系統的實時性與演算法復雜性之間的矛盾，設計了以高性能的dsp晶元tms320c6416為核心處理器，結合大規模可編程邏輯器件cpld進行邏輯控制以及現場可編程門陣列fpga對採集的視頻數字圖像做預處理的實時目標識別跟蹤處理平臺。
  15. Fpga ( field programmable gate array ) is a kind of programmable logic device

    Fpga屬於一種可編程邏輯器件，晶元內部以陣列狀排列各種可配置邏輯塊。
  16. The system used hight - performance dsp ( tms320c6202 ) to realize the real - time image object tracking algorithm, used large - scaled programmable logical array cpld to control logic and field programmable gate array fpga to preprocessing the image

    其中運用了高性能dsp （ tms320c6202 ）完成實時圖像目標處理演算法，並結合大規模可編程邏輯陣列cpld進行邏輯控制和現場可編程門陣列fpga對採集的視頻圖像做預處理，滿足了系統的實時性。
  17. There are many encryption algorithms. even for one algorithm, rsa, for example, the architectures of different modular length rsa are not same. the dissertation focuses on the research and design of the reconfiguration in the encryption application using fpga

    在現場可編程邏輯陣列fpga上，實現多種加密演算法以及不同長度密鑰的rsa演算法的可重構，在目前對開展可重構計算技術在加密方面的應用基礎研究和研發有自主版權的加密硬體技術有一定的意義。
  18. For the high - speed digital signal processing, the structure of fpga and dsp is widespreadly adopted. dsp is more featured in the implementation of complicated algorithm, while field programming gate array ( fpga ) shows more advantage in its flexibility of design, simplicity of system configuration, modification and maintenance. in the paper, the hardware system of the spaceborne radar is based on the structure of fpga and dsp, of which the signal processing part is accomplished with one fpga chip and multi dsps

    Dsp適合完成結構復雜的演算法;現場可編程邏輯陣列（ fpga ）適合完成高效、演算法固定的任務;與專用集成電路（ asic ）相比， fpga優點主要在於其很強的靈活性、可在線配置、修改和維護方便等優點。本文工程中的星載雷達信號處理和控制系統就是採用dsp + fpga的方式。其中信號處理採用的是xilinx公司的virtex -和virtex系列fpga和多片analogdevices公司的tigersharcts101的硬體電路結構。
  19. The real - time target track processing system is designed which is constructed by the high performance dsp chipset tms320c6416 as the core digital processor, the huge reprogrammable logic chipset cpld as the system logic control and the field reprogrammable array fpga as the image preprocessing chipset to sampled video digital image

    為了解決演算法復雜性及滿足工程實時性，設計了以高性能的dsp晶元tms320c6416為核心處理器，結合大規模可編程邏輯器件cpld進行邏輯控制以及現場可編程門陣列fpga對採集的視頻數字圖像做預處理的實時目標識別跟蹤處理平臺。
  20. It details the ic design process and vlsi circuits, including gate arrays, programmable logic devices and arrays, parasitic capacitance, and transmission line delays

    它詳細規定了集成電路設計過程和超大規模集成電路電路，包括門陣列，可編程邏輯器件和陣列，寄生電容，及輸電線路的延誤。
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