編號控制 的英文怎麼說

中文拼音 [biānháokòngzhì]
編號控制 英文
block control
  • 編 : Ⅰ動詞1 （編織） weave; plait; braid 2 （組織; 排列） make a list; arrange in a list; organize; gr...
  • 號 : 號Ⅰ名1 （名稱） name 2 （別號; 字） assumed name; alternative name3 （商店） business house 4 （...
  • 控 : 動詞1 （告發;控告） accuse; charge 2 （控制） control; dominate 3 （使容器口兒朝下 讓裏面的液體慢...
  • 制 : Ⅰ動詞1 （製造） make; manufacture 2 （擬訂; 規定） draw up; establish 3 （用強力約束; 限定; 管束...
  • 編號 : 1 （按順序編號數） number 2 （編定的號數） identifier; serial number; 編號次序 numeral order; 編...
  • 控制 : control; dominate; regulate; govern; manage; check; cybernate; manipulate; encraty; rule; rein; c...
  1. In designing analogic circuit, we adopt programmable filter max262 to meet the system ' s command. after the step, we can make the signal ' s frequency width is wider and noise level is lower. to make the signal ' s amplitude to meet the analogic to digital device ' s command, we adopt the max551 to finish the gain control

    在模擬電路部分，採用可編程濾波器max262 ，這樣就滿足了該數據採集裝置所採集的信號的頻率范圍較寬以及具有較低的噪聲水平的要求，為了使采樣到的信號的幅度滿足後面a d轉換器的要求，採用max551對采樣到的信號進行調理（增益控制） 。
  2. Pre - data gathering module achieves the collection and communication of sixteen - route temperature signal. speed measuring and controlling module realizes the control of refolw soldering transfer speed by manipulating transducer. on - off outputting module fulfills calefaction control of calefaction tube by solid state relay. above position operator software programs by delphi, and realizes pid parameter automatic timing and no - oversnooting temperature control. software has friendly interface, convenient operation, complete functions

    前置數據採集模塊完成16路溫度信號的採集和通訊；速度測量模塊與速度控制模塊通過控制變頻器來調節迴流焊的傳輸速度；開關量輸出模塊通過固態繼電器對加熱管進行控制；上位機軟體採用delphi編程，實現了pid參數自整定以及無超調的溫度控制。
  3. Identifies the caret width, in pixels, for edit controls

    標識編輯控制項的插入符號寬度（以像素為單位） 。
  4. The system comprises three modules : the first is the ccd driver module, which controlled with cpld. programming the cpld to produce ccd driving pulses and synchronized communication signals. after preprocessing, the output video signals are transmitted into high resolution adc module, in which they are converted into digital signals, and then processed in arm processing module

    整個系統分為三個模塊: ccd驅動模塊的核心是一片復雜可編程邏輯器件（ cpld ） ，對其編程產生ccd的驅動脈沖及同步控制信號;視頻輸出信號經預處理后，由高精度ad轉換模塊進行采樣，將ccd輸出的模擬信號轉換成數字量;最後，將數據送入arm處理系統中進行后續處理。
  5. The main research advances can be summarized as follows : ( 1 ) study the signal processing ' s performances and methods of homing torpedo system comprehensively, in order to setting up a corresponding mathematical models ; ( 2 ) analyze the ocean channel ' s effects on the work of homing system, then found some models such as target echo signal, noise ( including background noise, target radiating noise, etc ), ocean reverberation. according to them, simulate the array signal ; ( 3 ) the system structure, every function blocks composing are studied and founded thoroughly. then, discuss methods of signal processing in time domain and airspace domain ; ( 4 ) program the simulation software of torpedo ' s homing system according to the simulation models and flow charts, which connected with torpedo ' s control part

    本文所作的主要工作及研究成果主要有以下幾個方面： （ 1 ）對自導工作過程中的信號與信息處理的基本理論與方法進行了較為全面的研究，為建立一個較為完備的自導模擬系統提供了理論基礎； （ 2 ）討論了自導系統工作過程中海洋通道對目標回波信號與目標輻射噪聲信號等的影響，建立回波信號的數學模型、環境場中的噪聲信號模型（包括海洋環境噪聲、目標輻射噪聲與魚雷背景噪聲等）與海洋混響模型，模擬產生了聲自導系統基陣接收到的回波信號與噪聲信號； （ 3 ）深入研究並建立了自導模擬系統的總體框架，給出各個具體功能模塊組成，討論了聲自導系統對信號的時域與空域處理，並結合模擬程序中陣列信號處理模塊，給出固定多通道波束形成的模擬實現過程； （ 4 ）根據系統的模擬模型與已建立的模擬流程圖編制了通用魚雷模擬器自導系統模擬軟體，通過網路與控制系統相連，組成完整的魚雷模擬器。
  6. Gets or sets the index number of the selected item in the

    控制項中要編輯的選定項的索引號。
  7. And the interfaces have analog input, analog output and digital input / output. we have used differently cards, such as pc - 6330d a / d card, pcl - 728 d / a card based isa bus, ipc - 5375 i / o card and so on. in addition, we select micro - stir switches and pressure sensors as sensor elements to inspect the system and choose relays and induction valves to control the bicycle pump and the motor

    總線採用isa內部總線；介面主要有模擬量輸入介面、模擬量輸出介面、開關量輸入輸出介面等，課題分別選用pc - 6330d型a d板卡、基於isa總線的型號為pcl - 728的d a板卡、型號為ipc - 5375的i o板卡；另外，課題選用了微動式行程開關、壓力變送器作為傳感元件檢測系統，選用繼電器、電磁控制換向閥實現對氣缸、電機的控制；採用vc + + 6 . 0編制控制軟體，實現了纖維鋪放技術的計算機控制。
  8. Code this control code of the recording s bit inside of the 16 the instruction to tell to put in the hdcd in the cd hdcd in the phonograph solution code, is central plains the number this of the high of that short restores out. like this, hdcd can in the cd of 44. 1 orotund number that khzs sampling frequency extreme limit inside, exceed the bandwidth 20 khzs re - appeared out

    在hdcd編碼錄音的第16bit中的這個控制代碼指令告訴放在cd唱機中的hdcd解碼器，把訊號中原本的那個短促的陡高音還原出來。這樣， hdcd就能夠在cd的44 . 1khz的取樣頻率極限內，把頻寬超過20khz的聲音訊號重現出來了。
  9. It designed signal amplifying circuit, frequency tricking circuit, data sampling and keeping circuit. the choice of 12 bits high accuracy a / d integrated data sampling card made program simply, high flexible and expandable. and to each error which is likely to occur in high voltage capacity type equipment during the monitoring, analysis and judgement are given

    在硬體電路實現上，注意選擇信號傳感器；合理設計了信號放大電路和濾波電路；設計了頻率跟蹤電路，數據采樣/保持電路；結合軟體控制選用了12位高精度的a / d轉換器，使軟體編程簡化且具有較高的靈和性和可擴展性。
  10. Chapter two describes the system ' s communication protocol and signal coding

    第二章主要講述了智能控制及安防系統的通信協議和信號編碼。
  11. Stoplights are red, yellow, and green, because traffic officials, early on copied the code system railroad engineers devised for track systems controlling the trains

    交通信號燈採用紅、黃、綠三種顏色，是因為早期的交通指揮官模仿鐵路工程師所設計的用於鐵道系統控制火車的編碼系統。
  12. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  13. More and more people begin to attach importance to its potence gradually. according to the basic principle of vbi, this paper acquires related experience from the advanced technique for delivering of control signals during the period of vbi. it introduces a scheme using a single coaxial - cable to transmit video signals and control signals simultaneously, in which the key technique is the transmission of control signals in the vertical blanking interval of video signals

    本文根據場消隱期傳輸技術的基本原理，通過借鑒國內外場消隱期傳輸信號的先進技術和相關經驗，提出一種新型的綜合數據傳輸業務的應用電視，闡述了其圖像信號和控制信號共纜傳輸的總體設計方案，並結合bch糾錯編解碼技術和systemview動態模擬軟體，實現和驗證了控制信號在場消隱期間的穩定可靠傳輸。
  14. A arming control system of synchronous fitting missle is brough forward in this paper of which the arming control unit composes of the high speed digital signal processing chip dsp and fpga, and has better performance in speed and precision

    本文提出了一種雙聯裝導彈瞄準系統，其瞄準控制部分由高速數字信號處理晶元dsp和現場可編程門陣列fpoa構成，使得整個系統在速度和精度方面都具有較好的性能。
  15. Digital enhanced cordless telecommunications dect - common interface ; test case library - part 9 : abstract test suite for network layer ; fixed radio termination endorsement of the english version ets 300497 - 9 v 0. 3. 2 1

    代碼字符集;信息;編碼數據轉換;信息交流;字符集;數據處理摘要本標準規定了由128個字元控制字元和圖形字元，如：字母數字及符號組成的字符集以及它們的編碼表示。
  16. To extent the use of this 1c, some circuit blocks are added. in the design, digital circuits are used to process the signal and control the precision of coding. and some circuits are used in different time by several functions to reduce the number of transistors used and the dissipation

    電路設計中，為了便於信號處理以及控制編碼精度，採用數字的方法進行量階和預測碼的計算；同時，為了減小電路規模，採用了時分復用的概念，用同一部分數字電路實現量階調整和預測碼的生成，增加了編碼精度，減小了電路的規模和功耗。
  17. Further investigated and analyzed composition structure and flow data that dsa ' s formation of image is systematic at first in this paper, carried on intact summing up to the data in the system, having given out the plan of design of high speed and large capacity data channel of digital formation of image system of x - ray ; deeper discussion of control way on sdram, give solution that many pieces of sdram works togetherses of realizing heavy capacity, designing of heavy capacity deposit board realize storing at a high speed to vision data by frame on the basis of this ; through further investigations of interface of pci bus, optimize back end state machine design and urge procedure making with lower, giving intact pci interface scheme that realize high speed dma data transmission and satisfy request of video transmitting ; further investigate the figure systematic design method of programmable logic devices, due to the difficult point of drifting about of enabled signal in fifo in common use and setting up and keeping of output signal, method has been proposed of improving stability of system making use of signal utilizing the phase locking ring in fpga to offer a lot of clocks to move thus realize coordinating the data between every module of system to transmit at a high speed by making use of fifo

    本文首先對數字減影血管造影（ dsa ）成像系統的組成結構和數據流向進行了深入研究和分析，並對系統中的數據流向進行了完整的歸納和總結，給出了x線數字成像系統中的高速大容量數據通道的設計方案；在對sdram的控制方式做了深入探討后，給出了實現大容量多條sdram共同工作的解決方案，在此基礎上設計了大容量幀存板實現對圖象數據進行高速存儲；通過對pci總線介面的深入研究，優化後端狀態機設計和低層驅動程序開發，給出了完整的pci介面方案實現高速dma數據傳輸，完全可以滿足視頻傳輸要求；深入研究了基於大規模可編程器件的數字系統設計方法，針對通用fifo使能信號漂移、輸出數據難于建立和保持等設計難點，提出了利用fpga中的鎖相環提供多個時鐘相移的信號來提高系統穩定性的解決方案，從而實現利用fifo來協調系統各模塊之間的數據高速傳輸。
  18. Above all, [ 12 : 8 ] harming error correction theory is mentioned in this paper. the edac circuit designed by vhdl can works normally at different frequency of the cpu clock such as 66mhz 50mhz 40mhz 33mhz. the edac function of the circuit can also be disabled by software tool. meanwhile, some basic devices such as and logic, or logic, not logic and some small scale integrated circuits are also integrated in the fpga

    本論文闡述了12 ， 8漢明碼糾錯設計過程，採用vhdl語言實現糾錯編碼器（ edac ） ，本設計能夠適應cpu時鐘信號clk2的不同頻率，如66mhz 、 50mhz 、 40mhz 、 33mhz ，並且能夠通過軟體的控制使fpga的糾錯編碼功能關閉。
  19. This lets you use user - coded control statements or xmi descriptions of cobol copybook members to supply information on additional fields, long java - style names, and data types

    這使得您可以使用用戶編碼控制語句或者cobol代碼庫編號的xmi描述來提供關于附加欄位、長java風格名稱和數據類型的信息。
  20. The scanning converter comprises five parts : video signal decoding, data reconstruction, progressive video signal encoding, control signal producing and communication

    掃描轉換器包含了電視信號的解碼、解碼后數據的重構、逐行信號編碼、控制信號的產生以及通信五部分。
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