緩沖單元 的英文怎麼說

中文拼音 [huǎnchōngdānyuán]
緩沖單元 英文
buffer cell
  • : Ⅰ形容詞1 (遲; 慢) slow; unhurried 2 (緩和; 不緊張) not tense; relaxed Ⅱ動詞1 (延緩; 推遲) d...
  1. First, it is compressible and cushiony ; second, it can be transported to a long distance with a little power loss ; the last, its flux and velocity of flow are quite high, so the reaction time of the operators can been considerably shortened. aiming to solve the problems of vibrating machinery such as short life - span, poor cushion and high energy consumption, the writer, on the basis of characteristic of pneumatic mentioned, contrives a set of valve controlled pneumatic vibrator, which has larger output vibrating force and longer life - span with simple structure. then, it is applied to drive a vibrating screen and the result is fairly well

    文中針對氣動技術本身的特性及優點,如:可壓縮,具有性;能耗損失小,便於遠距離輸送;流量大、流速高,執行件響應速度快等,以解決振動機械在應用過程中的、能耗以及使用壽命等問題為目的,設計出一套輸出激振力大、結構簡、使用可靠的閥控氣動激振器,並將其成功地運用到振動篩上,取得了較好的效果。
  2. The design of each functional module, including the bridge selected module, mlb slave state machine, buffer, ahb master state machine, arbiter. 4

    各功能模塊的設計,包括橋選擇、 mlb從狀態機、區、 ahb主狀態機,仲裁器; 4
  3. A novel pwm dc converter with snubber cell

    一種新的帶有緩沖單元的脈寬調制式直流變頻電路
  4. The principal difference being that changing the buffer associated with a compilation unit updates the corresponding elements of the java model

    ,其原理不同之處在於,更改與編譯相關的區更新了java模型的對應素。
  5. Every column in sensor array work in parallel and have their own cds noise reducing circuit. the signals after fpn reducing are output from the output buffer amplifiers

    傳感陣列中各列感光的傳感信號并行輸出,分別由對應的相關二次采樣電路進行降噪處理,去除固定模式噪聲后的信號通過輸出放大電路進行輸出。
  6. Is the length in bytes of the data buffer

    是數據區的長度,以位組為位。
  7. Read requests typically require " x " bytes to be placed in a single i o buffer

    讀請求通常要求將「 x 」個位組放在一個獨的i / o區中。
  8. By default mmus are implemented and they are constructed of 64 - entry hash based 1 - way direct - mpped data tlb and 64 - entry hash based 1 - way direct - mapped instruction tlb

    默認的存儲器管理實現由基於64個散列入口的通道直接映射的數據后備式轉換區和基於64個散列入口的通道直接映射的指令后備式轉換區組成。
  9. That contains the size, in bytes, of the receive buffer

    包含接收區的大小(以位組為位)的
  10. Concretely, on the basis of describing the communication specification of arinc 429 with enhanced parallel port ( epp ), the standard and the module application of dsp and cpld, the thesis has proposed the design of the arinc 429 technology based on dsp system. at first, the function and the application of each module of the system and the operation principle of high - performance cmos bus interface circuit hs - 3282 chip which forms the main body of the data diversion of the interface module are introduced. secondly, the hardware structure of the interface module is described in detail, mainly including data latch and buffer circuit, choice circuit of transmission rate, etc. and then the design philosophy and flow charts of the software are fully discussed, such as the basic requirement of software, the design and realization of the function

    本文在簡的論述了pc並口協議( epp )與dsp之間的通信方法、 cpld模塊邏輯控制應用和arinc429的通訊規范的基礎上,給出了基於dsp的arinc429通訊介面的設計方案:對通訊板中各模塊的功能和應用以及構成數據轉換主體的總線介面晶hs - 3282的工作原理做了說明;介紹了本設計所用的dsp和cpld的功能概況;詳細敘述了通訊板介面模塊的硬體結構設計,其中,對數據電路、數據傳輸速率選擇電路、邏輯控制電路等各關鍵點做了重點介紹;具體闡述了軟體設計思想及流程圖,包括軟體的基本要求和功能的設計與實現;接著從埠譯碼、 i / o通道、電平轉換電路等方面進行了介面模塊的軟、硬體調試;最後,給出了測試結果,對研製工作做了總結,對本設計的優缺點各做了評述。
  11. A processor architecture is disclosed including a fetcher, packet unit and branch target buffer

    母案摘要:揭露一種包含指令取器、封裝及分支目標器的處理器架構。
  12. In such systems, queuing technology provided the buffering and control mechanism needed to support orderly and properly sequenced transaction flows between individual processing elements

    在這種系統中,排隊技術提供了為支持各個處理之間有序的交易流動而需要的和控制機制。
  13. The content of the electricity transforming of the system with profibus includes the designing of signal detecting and dealing system, the developing of the major cache unit machine control, the integration of the system diagnosis and data information, and the subordinate station diagnosis function

    基於profibus現場總線技術的濾棒儲存輸送系統電氣改造設計內容,主要從系統信號檢測與處理方式的改進設計、主體緩沖單元電機控制方式的改進設計、系統診斷及生產過程數據信息的集成設計和系統從站診斷功能設計等幾個方面講解。
  14. Gets or sets the size, in bytes, of the default label buffer

    獲取或設置默認標簽區的大小(以位組為位) 。
  15. Generators producing high purity nitrogen and air use the same psa principle, using an additional bed of activated alumina for air purification

    空氣純化由變壓吸附和氮氣組成。該設備主要用於從空氣中分離出廉價的氮氣,以供使用。
  16. Moreover, video control program to implement internal function of fpga is designed including video capture time sequence control, ping - pang frame buffer read and write time sequence control and lcd display time sequence control, and program ' s simulation and analysis is also provided. at last, this paper presents a portable iv ' s video processing system, and proposes three buffer strategy to control capture buffer. and a moving object detection algorithm of combing an adaptive background subtraction technique with a three - frame differencing is adopted

    設計了基於fpga系統結構的車載視頻顯示電路板;利用片機io口模擬i2c時序,實現了視頻解碼晶控制;利用fpga實現視頻控制,研究了採集通道時序控制、雙幀存ram讀寫時序控制及lcd顯示時序控制的方法,並進行了軟體模擬和分析;設計了車載視頻檢測系統方案,給出了管理採集區的三幀策略,採用綜合三幀差分和自適應背景相減的演算法實現運動檢測,連通體檢測去除虛目標,模擬實驗證明其有效性,同時分析了該演算法在dsp視頻檢測系統中的簡實現方法。
  17. String pooling allows what were intended as multiple pointers to multiple buffers to be as multiple pointers to a single buffer

    串池允許將作為指向多個區的多個指針用作指向區的多個指針。
  18. The origin for character cell coordinates in the screen buffer is the upper left corner, and the position of the cursor and the console window are measured relative to that origin

    格在屏幕區中的坐標原點為左上角,光標和控制臺窗口的位置相對于該原點進行計算。
  19. The screen buffer is an attribute of the console, and is organized as a rectangular grid of rows and columns where each grid intersection, or character cell, can contain a character

    屏幕區是控制臺的一個屬性,以由行和列組成的矩形網格的形式進行組織,其中每個網格交叉位置(字格)都可包含一個字
  20. Base on the theory analysis of the superconducting rsfq digital circuit model, wrspice is used to do time domain simulation of superconducting rsfq digital circuit in this paper, and superconducting jtl, buffer, rs flip - flop, t flip - flop, and or gate are acquired

    在超導rsfq數字電路模型的理論分析基礎上,論文中採用wrspice對超導rsfq數字電路進行時域模擬,得到了超導jtl傳輸線,器, rs觸發器, t觸發器,或門等基本邏輯電路以及電路參數。
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