脈沖邏輯電路 的英文怎麼說

中文拼音 [màichōngluódiànlù]
脈沖邏輯電路 英文
pulse logic circuit
  • 脈 : 脈名詞1. （動脈和靜脈的統稱） arteries and veins2. （脈搏的簡稱） pulse 3. （像血管的組織; 連貫成系統的東西） vein
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 電 : Ⅰ名詞1 （有電荷存在和電荷變化的現象） electricity 2 （電報） telegram; cable Ⅱ動詞1 （觸電） give...
  • 路 : 1 （道路） road; way; path 2 （路程） journey; distance 3 （途徑; 門路） way; means 4 （條理） se...
  • 邏輯 : logic
  • 電路 : [訊] circuit （ckt）; electric circuit; electrocircuit電路板 circuit board; 電路保持 guard of a c...
  1. If all errors belong to single or multiple temporary 0 1 - error or stuck - at - error produced by one module, then these errors can be corrected effectively. the results obtained from the simulation validate the correctness of the cl - acl structure. analytic results show that the delay of the cl - acl structure is dramatically less than that of a dmr structure using alternating - complementary logic mode

    這些粒子所引起的干擾不僅將改變存儲單元的邏輯值，而且將導致邏輯電路產生瞬時輸出脈沖，如果這些脈沖在某個關鍵的時間段里產生，比如在時鐘或數據的變化過程中，那麼它們將間接地使其它電路的狀態產生變化。
  2. According to the requirements of static compensator ( statcom ) to triggering pulse generator, an autonomous triggering system for statcom was developed based on complex programmable logic device ( cpld )

    針對靜止無功補償器（ statcom ）對觸發脈沖發生電路的要求，利用復雜可編程邏輯器件（ cpld ）開發了一種自治型statcom觸發系統。
  3. By analyzing the equivalent circuit of statcom, the basic requirements to the triggering system was pointed out, and the cpld - based functional structure for triggering pulse generator was established

    通過對statcom工作原理與等效電路的分析，指出了statcom對其觸發系統的基本要求，建立了基於cpld的觸發脈沖發生電路的功能邏輯結構。
  4. To realize nolinear excitation controller, it must be improved that the disposal speed of nolinear excitation control " s signal. with analyzing and comparing all kinds of microcomputer excitation controller, a new microcomputer excitation control scheme is offered that is based on dsp controller while the cpld chip is utilized for realizing the function of pulse trigger. it is described in detail that the method of realizing controllable silicon digital logic by verilog hardware describe language and the designed digital pulse trigger " s veracity was validated by digital simulation

    論文進一步針對非線性勵磁控制要求信號處理速度高、信息量大的特點，在對目前微機勵磁控制器分析基礎上，提出採用dsp控制器晶元作為核心處理器的微機勵磁控制器的解決方案，運用復雜可編程邏輯器件cpld晶元實現可控硅同步脈沖觸發單元，並簡要說明了verilog硬體描述語言和數字脈沖形成邏輯的方法，通過電路數字模擬對所設計的數字觸發單元進行了驗證。
  5. The important part in photoelectric transform circuits is design of driving circuits and signal processing circuits about linear ccd. the time order driving circuit of ccd are designed and debugged with cpld ( complicated programmable logic device ), which make the whole driving circuit ' s volume very small, shorten design period, modify design at any time, and enhance reliability and agility of circuit

    在設計過程中，採用了一種復雜可編程邏輯器件（ cpld ）設計線陣ccd驅動脈沖電路的新方法，只對器件進行重新編程，在不改變任何硬體的情況下，就可以實現驅動器的更新換代，非常適合線陣ccd脈沖產生電路的設計研究，具有高集成度、高可靠性、開發時間短、投資少等優點。
  6. In this paper we discuss mca circuit, the sequential logic for mca data collection, for the setting of the uld, lld and the gain of pga, as well as the combinational logic for decoding circuits of the computer interface, based on cpld

    本文詳細論述了利用cpld實現的脈沖幅度多道電路及其數據採集的時序控制邏輯、閾值設定和程式控制放大倍數設定的時序控制邏四川大學碩士學位論文輯、以及與計算機介面的譯碼電路等組合控制邏輯。
  7. In order to get data, the plane use the way of comparative between the black line and white line. the device is composed of the pulse producer, system controller, signal processor, logic analyzer, interface circuit and electrical machinery driver. this device could follow the tracks of the plane graphic border automatically

    跟蹤裝置運用黑白交界圖線比較法取得數據，由步進脈沖發生器，系統控制器，信號處理器，邏輯判別器，介面電路，電機驅動器等組成，可對平面圖形邊界進行自動跟蹤控制。
  8. The paper analyses its key circuit and software program structure. this full - digital controller is made up of dsp and implements single neuron adaptive pid computation, current pi computation, logical determination, pulse - fire and procession of protective signal etc. it also improves the reliability and availability of this control system

    本課題對控制器主要的電路結構及程序結構進行了分析，以dsp為核心組成的全數字式控制器完成了電流pi演算法計算，單神經元自適應pid演算法計算、邏輯判斷、脈沖觸發以及系統保護信號的處理等，提高了控制器的可靠性和可操作性。
  9. To solve this problem, quick range measurement technology was researched based on the method of propagation delay and working principle of cpld. a time measurement circuit with an accuracy of ? 0. 2m was designed and accomplished. it could finish the whole measurement process in 80ns after the bounced pulse was received

    針對該問題，基於傳遞延時插入法和cpld的工作原理，對快速測距技術進行了研究，研製了一種能實現收到回波脈沖后80ns內完成測距，測距精度0 . 2m的計時電路，並將該電路集成於一片可編程邏輯器件中，減小了電路面積和功耗，增強了抗干擾能力。
  10. The clock and data pulsation signals from upper sensor heads can be received using pin diode, then, amplified and inverted in logical control unit for the purpose of cpu operation. hereinafter, the digital signal will be delivered into the central processing unit ( cpu ) for related calculation, and meanwhile transmitted to a d / a converter for signal recovery after filter and phase - shift circuit

    通過採用pin管接收從傳感頭傳遞下來的時鐘脈沖和數據脈沖信號，並將它們放大整形傳送到邏輯控制單元，產生邏輯控制信號，再將數字信號傳送給d / a轉換器，設計了濾波器和移相器電路，還原出了原始的被采樣信號。
  11. A design of the feeder terminal unit based on dsp is presented. an integrated prototype is composed of a 6 - channel voltage collector, a 6 - channnel current collector, a 16 - channel state collection a 2 - channel impulse collector, a data processing unit whose core is dsp, a general controller in which cpld is used

    系統通過6路電流採集、 6路電壓採集、 16路的狀態採集以及2路的脈沖採集獲取相應的數據信息；以高性能數字信號處理器tms320vc5402為核心構成數據處理單元；以高性價比的可編程邏輯器件epm7128為全局控制器；同時數據可以通過鍵盤和數碼管進行現場控制。
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