視頻字元信號 的英文怎麼說

中文拼音 [shìbīnzìyuánxìnháo]
視頻字元信號 英文
video character signal
  • 視 : Ⅰ動詞1. （看） look at 2. （看待） regard; look upon 3. （考察） inspect; watch Ⅱ名詞（姓氏） a surname
  • 頻 : Ⅰ形容詞（次數多） frequent Ⅱ副詞（屢次） frequently; repeatedly Ⅲ名詞1 [物理學] （物體每秒鐘振動...
  • 字 : Ⅰ名詞1 （文字） character; word 2 （字音） pronunciation 3 （字體） form of a written or printed ...
  • 號 : 號Ⅰ名1 （名稱） name 2 （別號; 字） assumed name; alternative name3 （商店） business house 4 （...
  • 視頻 : [物理學] video frequency （v f ）; vision frequency; visual frequency; video視頻變頻器[變換器] vi...
  1. This paper refers to several creation in compatibility with large volume of fed display and conversion of different video signal. it firstly used special central chip al300, designed correlative circuits, successfully developed vga full - color fed console system, compatible with resolution 1280 1024, achieved functions such as multi - video signal conversion and interleaving, met vga ’ s resolution of fed. it firstly designed and fabricated vga interface and separated video interface - - s - video, converting several video signals to 24 bits full - colored digital image signal in fed driving system, achieved separation of luminance signal and chromatism signal, enhanced the bandwidth of luminance signal

    首次採用平板顯示專用控制晶元al300 ，設計並製作了相關配套電路，支持的最高解析度是1280 1024 ，實現解隔行和多種視頻格式轉換的功能，滿足了fed顯示屏對vga解析度的要求。首次在基於fpga的vga級彩色fed控制系統中設計並製作了vga介面和分離電視信號s - video介面，可以將多種視頻信號變換為fed驅動系統可用的24位彩色數字圖像信號，實現亮度信號和色差信號的分離，提高了亮度信號的帶寬。
  2. The subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc. a / d decode module gathers analog tv signals and realize video decode ; fpga video processing module deals with the data after decoding and produces systematic logic control signal ; video data frame deposit module offers the buffering area to a large n umber of high - speed video data ; base clock produce module through input basic video signal offers system accurate relevant synchronous signal ; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly ; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing

    本課題主要完成了a d解碼模塊、 fpga視頻處理模塊、視頻數據幀存模塊、基準時鐘產生模塊、 d a編碼模塊、 i ~ 2c總線控制模塊等部分軟、硬體設計及調試。其中a d解碼模塊採集模擬電視信號實現視頻解碼； fpga視頻處理模塊對解碼后的數據進行去噪處理的同時還負責系統的邏輯控制；視頻數據幀存模塊為大量高速的視頻數據提供緩沖區；基準時鐘產生模塊通過輸入基準視頻信號為系統提供精確的相關同步信號； d a編碼模塊在視頻處理模塊的控制下把數字視頻數據轉換成復合電視信號供顯示用： i ~ 2c總線控制模塊模擬i ~ 2c總線時序實現對系統中編、解碼晶元的初始化。
  3. The bt819a of brooktree corp is selected for front - end video a / d transforming, bt852 as video d / a, and the tms320c6711 of ti corp. selected for h. 263 core algorithm processing in the system hardware design

    該系統硬體設計選擇了conexant公司的bt819a晶元為前端視頻採集a d晶元， bt852晶元作為後端視頻的輸出d a晶元，完成對視頻信號數字化和逆處理，為dsp對系統功能處理作好準備。
  4. It has application in dvd and htdv and dvb - c and video transmission in network, etc. two parts the principle of video reduced on mpeg - 2 standard and the designing of encoder and debugging on encoder are primarily expatiated on in this dissertation

    本文編碼器採用fujitsu公司的mpeg - 2編碼晶元mb86390用硬體來實現視頻信號的壓縮，編成mpeg - 2碼流，可應用於dvd 、數字電視、 dvb - c及視頻的網路傳輸等。
  5. Video - process chips on display adapters always have the digital interface which can support the panel monitor, the output port of most of display adapters only offer the analog signal interface

    雖然當前計算機顯卡視頻處理晶元中一般都有支持平板顯示器的數字視頻介面，但現在大部分的計算機顯卡的輸出仍然只提供模擬信號介面。
  6. Is a vesa standard data format that contains basic information about a monitor and its capabilities, including vendor information, maximum image size, color characteristics, factory pre - set timings, frequency range limits, and character strings for the monitor name and serial number

    是一種vesa標準數據格式，其中包含有關監視器及其性能的參數，包括供應商信息、最大圖像大小、顏色設置、廠商預設置、頻率范圍的限制以及顯示器名和序列號的字元串。
  7. There are several advanced functions in control system of fed driving based on fpga. the special al875 can support multi - display format from qvga 、 vga 、 svga to xga in the digital rgb graphics and video frequency. using vga interface and d / a conversion technology, it can monitor data signal and control signal real time. the control of buffer storage carry out seamless link by double frame memory refurbish. osd can control menu and text to adjust state by double display

    完成的基於fpga的新型fed驅動控制系統具有幾種先進的功能:採用專用於rgb圖形/視頻信號數字化的al875晶元，可以支持從qvga 、 vga 、 svga到xga的多種解析度的顯示格式;採用vga介面技術和d / a轉換技術，用於實時監控整個系統中的圖像數據信號和控制信號;採用乒乓刷新控制機制對緩存進行控制，實現數據讀寫操作的無縫連接;採用osd在屏顯示單元，實現控制菜單、文本在屏幕上的疊加顯示。
  8. It ’ s a 16 / 32bits risc cpu based on arm920t ip core, which is highly integrated and powerful. this cpu has a lot of peripheral interfaces and i / o ports, which will facilitate our system design. the asic ime6400 is a system level chip which supports the multi - channel mepg4 video / audio compression. in our design, it ’ s served as an video compression oriented co - processor working under the control of s3c2410x. s3c2410x will do the job of importing the other vehicle traveling data such as analog and switch signals

    在筆者設計的系統中， ime6400作為專門進行數字視頻信號壓縮的協處理器，與s3c2410x協同工作，完成視頻信號的獲取，壓縮等工作;同時利用晶元的片內外設（如ad轉換器和i / o口） ，完成汽車行駛過程中開關量和模擬量的獲取和存儲，以滿足一個記錄儀的基本功能需求。
  9. At present a new kind of tv set appears in the market. it " s based on the digital process technology, and we call it digital process tv set. it use various of the diagital methods to process the interlace, low field _ rate signal, include the deinterlace, field _ rate conversion and the methods of display enhance

    他的核心是利用各種數字的方法對隔行低場頻的模擬電視信號進行去隔行、提高幀頻、以及進行降噪和各種畫質增強的處理，極大的改善了畫面的質量。數字處理電視的核心是電視信號數字處理晶元。
  10. This image grab card uses saa7111 to translate the analogue signal to digital image data. after buffering in an fifo ram the data are read into computer by a universal pci interface chip, pci9052. finally the images are displayed on screen

    該視頻採集卡以fpga為邏輯控制中心，採用saa7111將四路視頻信號分別轉換為數字圖像數據，經fifo緩存后，由pci總線介面晶元pci9052將數據送入計算機，最後通過應用程序將圖像顯示出來。
  11. According the standard of digital video broadcasting for cable channel, this paper analyze, design and simulate a all - digital demodulator that receive high rate quadrature amplitude modulate ( qam ) signal in order to making the demodulator chip for qam signal that transmitted through the channel of cable television. the paper includes some contents as follows

    本文依照dvb - c傳輸標準，為了製作數字有線電視接收機中的正交振幅調制（ qam ）信號的全數字解調晶元，對qam信號的全數字解調器進行了分析、設計和模擬，主要包括以下內容：對數字下變頻進行了分析、設計和模擬。
  12. The chip of ks0122 is selected for vedio decoding and ad conversion with rgb digital vedio signal output

    其中kso122作為視頻解碼和模數轉換晶元，輸出rob數字信號。
  13. In this paper, analyzing and designing a high - speed video collection and processing system which is applied to the dynamic realtime image - dection sub system of the floating - precision tracking platform ( fptp ). and discussing the key technology in the video signal processing field, such as digital signal processing, cpld / fpga and dma

    本文基於某國防項目浮空精密跟蹤平臺的研究與設計，通過對該系統的動態目標實時圖像檢測子系統中高速視頻採集處理平臺的分析與設計，討論了現代視頻採集與處理系統中通常採用的一些關鍵技術，如數字信號處理晶元、大規模可編程器件、 dma傳輸。
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