解串列 的英文怎麼說

中文拼音 [jiěchuànliè]
解串列 英文
deserialize
  • 解 : 解動詞（解送） send under guard
  • 列 : Ⅰ動1 （排列） arrange; form a line; line up 2 （安排到某類事物之中） list; enter in a list Ⅱ名詞1...
  1. This algorithm is based on the 16 - fft about square root decomposition, and using the phase revolution unit replaces multiplication, and uses the serial butterfly operation unit. at last, gives the correspond realization measure in fpga

    本文根據一種基於平方根分解的16點fft演算法，採用相位旋轉因子取代乘法器，並利用串列流水蝴蝶運算單元給出了一種新的實現演算法，並介紹了其在fpga中相應的實現方法。
  2. 2. the add operation optical channel that can fulfill standing carry was set up, which solved the problem of uncertain carry - delay encountered in huge - numeral add operation with common successive earn

    2 、創建了「進位直達」加法器原理光路，解決了巨位數加法運算串列進位的不定長延時難題。
  3. The control area network - can belongs to the category of fieldbus. it is an actual effect support distribution type control or aserial communicatioan network in real - time - controlling, which was developed by the german bosch company for resolving the digital exchange between controller and measuring instrument in modern car of many casea

    控制器局域網? can屬于現場總線的范疇，它是德國bosch公司為解決現代汽車中眾多的控制與測試儀器之間的數據交換而開發的一種有效支持分散式控制或實時控制的串列通信網路。
  4. At the fore end a computer controls the scrambling circuit through serial communication

    在有線電視系統前端通過微機串列通信可以對加解擾的實現進行控制。
  5. The inversionless bm algorithm in rs decoder is implemented with serial mode, which avoids the inversion computation and only needs 3 finite - field multipliers. thus, the complexity of hardware implementation has been mostly reduced. a 3 - level pipe - line processing architecture is also used in the hardware and the coding circuit in rs coder is optimized by using the characteristics of the finite - field constant multiplier

    Rs解碼器的設計採用無逆bm演算法，並利用串列方式來實現，不僅避免了求逆運算，而且只需用3個有限域乘法器就可以實現，大大的降低了硬體實現的復雜度，並且因為在硬體實現上，採用了3級流水線（ pipe - line ）的處理結構。
  6. This thesis analyzed the error performance of mfsk and mpsk modulator in hf with optimal receiver, studied the shortcoming and strongpoint of several typical short - wave data transmission systems and their performance over fading and intersymbol interference channels. the theory and key technical of adaptive modem is discussed. in the last, an efficient modulation scheme - block coded modulation is introduced into hf radio systems to improve the efficiency of hf data transmission, this paper also proposes a hf data transmission system scheme composed of a block coded modulator and a decision feedback type adaptive equalizer

    本文在對短波數傳兩種常見調制方式fsk及psk最佳解調性能分析的基礎上，討論了幾種採用典型調制技術的短波數傳系統（如時頻調制、多進制頻移鍵控慢跳頻、 chess系統）原理、優缺點以及抗衰落和抗符號間干擾的性能；分析了自適應串列數傳系統抗短波通道衰落和多徑干擾的原理、關鍵技術；在本文的最後引入一種有望解決短波數傳系統低效率狀況的調制方式bcm -分組編碼調制，給出了一個採用bcm技術與自適應均衡技術相結合的短波數傳系統方案，並通過計算機模擬進行了初部驗證。
  7. This paper illustrates detailedly the thin groupware auto - adaptive recognition system ; it also illlustrates the procession of capture image and take indispensable foreclose to wipe off noise in order to get boundary easilyer. the recognition system uses " hough " transform method to make the recognition area orientation, and according to the unstable environment such as lights which leads to the change of the image ' s brightness, thresholds picture using an iterative selection method and then growing process for cell image segmentation based on local color similarity and global shape criteria, adaptively gets the best threshold to divide the washer off the background. the recognition system uses the classifier based on minimal - error - ratio bayes method to make decision after getting image characteristic

    本文詳細介紹了薄形組合件自適應識別系統；闡明了圖像的分通道自動採集過程，以及對採集到的原始圖像所進行的預處理方法。通過採用哈夫變換去除偽邊緣點的方法，有效地解決了識別區域的定位問題。針對裝配零件（主要是墊片）薄、小導致圖像信息少、識別難度大，以及材質不一導致採集到的組合件圖像亮度波動等問題，提出了使用最佳閾值迭代法和使用種子填充的圖像串列分割技術，自適應地找出最佳閡值，使墊片和背景分離，從而提取墊片數目信息。
  8. The transverse hierarchy accords with the serial decision process of bringing forward decision problem, solving problem, evaluating project and bringing forward project

    縱向分佈模式映射了決策過程中問題提出、問題求解、方案評估和決策結果生成的串列求解過程。
  9. The tramsission rate exceed to the range of isa bus, moreovcr the pci bus can be competent for the rate request. the card makes use of the total line in pcicontroller, the slice of fifo, fpga and super - speed a data correspondence chip, which can solve the transmission stream and total line in pci connecting problem. and realizes the mpeg - 2 deliver to flow with establish outside delivers

    此速率超過了isa總線所能支持的傳送速率，而pci總線能夠勝任這一要求，由此確定節目傳輸流發送卡採用pci總線。此卡利用pci總線控制器、 fifo晶元、 fpga晶元、高速串列數據通信發送晶元，解決傳輸流與pci總線之間的介面問題，實現了mpeg - 2傳輸流與外設的高速數據傳輸。
  10. 4 completing the joint - debug on the system which is made up of the serial transmission system or the parallel transmission system with the mpeg - 2 multiplexing / de - multiplexing equipments

    4 ：完成了將串列傳輸系統和并行傳輸系統同mpeg _ 2復用/解復用器所組成的系統的聯合調試。
  11. This card largely depends on three integrate chips to fulfill its function : 1 ) nic control main chip, corresponding the mac sublayer of ethernet, to realize csma / cd media access protocol, manage the sending and receiving buffers integrated on the chip and provide motherboard pci interface. 2 ) serdes ( serializing and deserializing ) chip, corresponding pcs and pma sublayers in ethernet, mainly to complete 8b / 10b coding and convert 10 bits parallel data to serial data, and convert them again at the receiving end. 3 ) fibre transceiver unit, completing light - electrical conversion of seri

    該網卡主要由3塊集成的晶元完成其功能，分別是i ）網路控制主晶元，對應于以太網的mac子層，主要完成csmaicd介質訪問協議，管理片上集成的發送和接收緩沖區，並提供和主板p0總線的介面： b ） s rd s （串列解串列化器）晶元，對應于以太同的pcs和pma子層，主要完成sb lob編碼並將10位并行的數據轉換為串列數據，在接收端完成相反的功能：涌）光纖收發器，完成串列數據的光電轉換功能。
  12. While executing the program, we memorize all the values of each array variable. the analysis will stop if data dependence is found

    動態測試就是在解釋執行程序的同時，記錄串列程序對數組元素的訪問，如果發現數據相關就終止測試。
  13. Technical points of hardware design single chip micro - controller dtmf / fsk code & decode flash memory ps / 2 serial port interface rs - 232c serial interface 4

    硬體電路設計單片機技術dtmf fsk編解碼技術flash技術ps 2串列口技術rs - 232c串列通訊介面技術4
  14. The serializer and deserializer moduls in the ftlvds chip are designed by the way of standard cell design approach. the paper emphatically discusses the tradeoff and the implementation of several clock synchronization modes and circuit structures, and makes a lot of verilog simulation and verification on the circuits designed

    串並模塊串列化器和解串列器採用標準單元的方法設計，論文討論了對幾種時鐘同步模式以及串並轉換電路結構的權衡和實現，並對所設計的電路結構進行了verilog模擬驗證。
  15. At the same time the author makes a deep research into the serial communication of the controlling signals of the sonar, the dynamic displaying of the image as well as the image post - processing and classification for the sake of sonar intelligentizing and the computer aided classification

    本文以投入正樣機研製的獵雷聲吶為背景，在著力解決工程實際問題的同時，對聲吶設備中控制信號的串列通信、聲納圖像的動態顯示以及後置圖像處理與識別做了較為深入的研究。
  16. We found that porphyran is a kind of good material for optical limiter. but to date no materials have exhibited strong enough nonlinear response to protect sensitive optical elements from laser - induced damage., we researched the graded density limiter and tandem limiter

    為解決現有非線性材料的非線性不能達到有效激光防護效果的問題，我們又研究了串列光限幅器件及濃度剃度光限幅器件的光限幅效率的影響因素。
  17. The double differential cross section ( ddx ) of neutron emission from 51v at 10. 26 mev neutrons was measured using normal and abnormal fast neutron tof spectrometers on hi - 13 tandem accelerator in china institute of atomic energy ( ciae ). the problem of influence from breakup neutrons of the d ( d, n ) neutron source on secondary neutron spectra was successfully solved

    用中國原子能科學研究院hi - 13串列加速器上的常規和非常規快中子飛行時間譜儀，測量了10 . 26mev中子引起~ （ 51 ） v的次級中子雙微分截面，成功解決了d （ d ， n ）中子源中破裂中子對次級譜的影響。
  18. It can interface with single chip computer expediently and transmit data by rule and line. oscillator in the infrared transmitting circuit that consisted of ne555, and can used to modulates the output from serial port of single chip computer. the integrated infrared receiver can demodulates, filter and transmit the signal to single chip computer

    紅外線西北口二j匕大學悶成d匕學位咭侖文發送電路的振蕩器由ne555構成，它可對串列口輸出信號進行調制，一體化的紅外接收頭對紅外信號進行解調、濾波和整形，再送單片機處理。
  19. It consists of two parts : channel modulator ' s controlling system and the receiver ' s controlling system, including the interface designing of the demultiplexer, the controlling of the channel demultiplexer, if modulator, tuner, the setting and transmitting of the system parameters, and the real - time monitoring of the whole system, etc. based on the descriptions of the scheme of bdb - t and the principles of controlling circuits, this paper presents the hardware and software designing methods of the controlling circuits, and realizes a powerful, multifunctional and reliable controlling system which can automatically record the operational states of the system and communicate with other personal computers through a rs - 232 serial interface

    控制系統是實現整個傳輸系統的關鍵部分，它分為通道調制器控制系統和接收機控制系統兩大部分，其中包括了通道解復用器用戶介面設計、對通道解復用器的控制、系統傳輸參數的設置與傳送、中頻調制器的配置、數字調諧器的配置，以及對整個系統的實時監控。本文在闡述了bdb - t方案及其各部分電路的控制原理的基礎上，詳細描述了控制系統的硬體電路設計和軟體實現方法，實現了一套功能完善、性能穩定且具有自動記憶功能的控制系統，同時該系統通過rs - 232串列介面可以實現與計算機的串口通信。
  20. The full chip can be partitioned to four modules, lvds driver, lvds receiver, serializer and deserializer. we implement these modules with different approaches based on their fuctions and characters

    晶元可劃分為lvds驅動器、 lvds接收器、串列化器和解串列器四個模塊。
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