觸發延遲 的英文怎麼說
中文拼音 [chùfāyánchí]
觸發延遲
英文
trigger delay-
A continuous film record can be built up by taking a series of single pictures of successively increasing values of the delay period between the instigation of the event and the instant of the flash.
可依次增加動態現象的觸發與閃光之間的延遲周期，以拍攝一系列單張照片，用以構成連續的影片紀錄。The modulating signals of firing delay angle at the rectifier and firing lead angle at the inverter, and the excitation voltage are chosen to be control variables. the offset of the current of dc line and the extinction angle and the power angle of generator are chosen to be control outputs. then a nonlinear controller is designed for the system under study according to direct feedback linearization theory
以整流側觸發延遲角的調節信號、逆變側觸發超前角的調節信號以及發電機勵磁電壓作為控制變量，以直流線路電流、逆變側關斷角以及發電機功角的偏移量作為目標輸出，用直接反饋線性化方法設計了系統的非線性控制器。This paper studied the effects of lag value 0ms - 900ms ontask performance in a desktop cve system
操作的執行時間與操作被用戶觸發的時間兩者的差值被稱為本地延遲值。4. demonstrating the structure and design of the counter + delay - line module, by which the pulse waveforms with given pulse delay and pulse width delay can be generated
4 .設計計數器+延遲線模塊的組成及方案，並據此實現根據觸發信號產生的具有一定脈沖延遲和脈沖寬度的脈沖波形數字信號。The results of calculations and experiments show that the delay and jitter increased as the percentage of sf _ ( 6 ) in sf _ ( 6 ) - n2 mixtures increased. the results of experiments show that the delay of sf _ ( 6 ) - ar follows the same rule. the u _ ( th ) u _ ( sb ) increased as the percentage of sf _ ( 6 ) in sf _ ( 6 ) - n _ ( 2 ) mixtures increased
B ：等u _ w條件下電脈沖觸發火花隙的觸發延遲時間（ t _ d ）及其抖動（ t _ j ）隨混合氣中sf _ 6含量上升而上升，且場利用系數對這一規律沒有影響。( 2 ) the mechanism of laser triggered multi - stage multi - channel switch was studied. the results of experiments and calculations show that the delay and jitter decreased exponentially as the working voltage increased. the delay and jitter decreased as the gas pressure increased ( t _ ( d ) p ~ ( - 1 ) if e / p > 0. 8 ( e / p ) _ ( lim )
B ：觸發延遲與聚焦透鏡焦距「 z一pinch ， ，加速器閉合開關技術研究之間存在一定的依賴關系，以nz為工作介質時焦距增長觸發延遲上升，欠壓比越大觸發延遲對焦距的依賴關系越弱;以nz / sf 。Trigger gate delay
觸發門脈沖延遲The input voltage of the piezoresistive transducer, gain, sampling frequency and negative delay can respectively be graded through programming. the stored system is specially designed to have two modes of trigger ( namely, external trigger through wire breakage and inner trigger through overpressure signal ), reading software and interface circuit that are of
該測試系統可通過編程選擇傳感器供電電壓（兩檔） 、放大倍數（四種） 、采樣頻率（四種） 、負延遲（四種） ；同時具有斷線外觸發和超壓信號內觸發兩種觸發方式；讀數的軟體和介面電路都具有串併兼容特性；系統還具有狀態自檢和定時上電等功能。Dj3032 supply a positive trigger pin. build - in delay time is about 3 sec. el frequency select by op1 and op2. please refer el frequency select table
Dj3032提供1正觸發輸入腳，內建延遲時間約3秒鐘， dj3032以op1 、 op2來選擇el頻率，請參考el頻率選擇表。The content of fpga is downloadable via prom, jtag or the special port on chip by xilinx software. the module can delay input signals from 0ns to 1. 8us stepping by 25ns. it ' s precision is 25ns
插件經過測試，能在0 71時鐘周期之間，以一個時鐘周期為步長實現對輸入信號的可編程延遲，延遲精度為25ns ，滿足觸發判選系統總觸發邏輯對齊來自各個探測器觸發子系統信號的要求。The main contribution of the thesis is seen as follows : aiming at the fault with slow speed and high power dissipation of the conventional phase - frequency detector, a high speed and low power dissipation phase - frequency detector is designed by modifying the structure of the single phase lock dynamic d flip - flop and adding the delay cell in the feedback loop to eliminate the phase detector ’ s dead zone effectively
論文的主要貢獻為以下幾個方面: 1 .針對傳統鑒頻鑒相器速度慢、功耗高的缺點，改進了單相時鐘動態d觸發器的結構，設計出了一種高速低功耗的鑒頻鑒相器，在反饋迴路上加入延遲單元，能有效的消除鑒相死區。分享友人