計算寄存器 的英文怎麼說
中文拼音 [jìsuànjìcúnqì]
計算寄存器
英文
calculating register- 計 : Ⅰ動詞1 (計算) count; compute; calculate; number 2 (設想; 打算) plan; plot Ⅱ名詞1 (測量或計算...
- 算 : Ⅰ動詞1 (計算數目) calculate; reckon; compute; figure 2 (計算進去) include; count 3 (謀劃;計...
- 存 : 動詞1 (存在; 生存) exist; live; survive 2 (儲存; 保存) store; keep 3 (蓄積; 聚集) accumulat...
- 器 : 名詞1. (器具) implement; utensil; ware 2. (器官) organ 3. (度量; 才能) capacity; talent 4. (姓氏) a surname
- 計算 : 1 (求得未知數) count; compute; calculate; reckon; enumerate 2 (考慮; 籌劃) consideration; pla...
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A computer storage position or register, whose contents identify a particular element in a table
一種計算機存儲器單元或寄存器,它的內容標識一個表中的特定元素。The part of execution in which an operand or instruction is read from main stora ge and written into a control unit or arithmetic unit register
執行過程中的一個階段所需的時間,在此期間,計算機從主存儲器中取出指令或操作數,並將其存入控制器或運算器的寄存器中。Computer control register
計算機控制寄存器Traditional methods such as emulation can do little about it, it has to introduce some new arts. on the path of modern computer and cpu designing, the registers, level 1 cache, level 2 cache on the chip and level 3 cache on the mainboard, plus ram, hard disk or floppy disk or flash disk, make up of the modern multi - hiberarchy storage architecture
現代計算機和cpu設計中, cpu片內的寄存器、一級高速緩存( level1cache )和二級高速緩存( level2cache ) ,主板上的三級高速緩沖,再加上主存,外存(硬盤、軟盤、電子盤等) ,構成了現代計算機的多級存儲體系結構。The model, in this case, is the high - level language program - which, like all useful models, hides irrelevant detail about the idiosyncrasies of the underlying computing technology such as internal word size, the numbers of accumulators and index registers, the type of alu, and so on
這種情況下,模式就是這個高級語言程序,它就像所有有用的模式那樣,隱藏了潛在的計算技術特性上的相關細節(比如內存字元大小,累加器的個數,索引寄存器, alu算術邏輯單元類型等等) 。Some computers have several fast registers which can be used to hold temporary results.
某些計算機有若干快速寄存器,它們能用來保存中間結果。The complete state of a computer, memory contents registers, flags, etc. at a selected instant of time
在選定瞬時計算機、內存內容、寄存器、標志等的完整狀態。In this paper, the methodology and implementation with hdl of design based reconfigurable architecture are discussed in detail, which includes the implementations of algorithms circuit, register file with controllable node, decoder, interface and main controller. from the introduction of design process of every module circuit, we can see easily some general feature of vlsi design with hdl
在此基礎上詳細討論了基於可重組體系結構的密碼晶元設計方法和各電路實現的結構圖,包括演算法電路、可控節點寄存器堆、譯碼電路、介面電路和主控模塊電路等。通過對各個模塊設計過程的介紹,闡明了使用hdl語言設計超大規模集成電路的一般特點。Vector registers were first used on expensive, high - performance supercomputers but are now becoming available on microprocessors where they are used to great advantage in intensive graphic operations
向量寄存器最初是用在昂貴的、高性能超級計算機上,但現在也用於微處理器,它們在密集的圖形操作中具有很大優勢。A typical calculator chip from rcl semiconductor inc, c9821, is referenced and developed. the chip of the calculator consists of several function units such as rc oscillator, power management module, microprogrammed control unit ( mcu ), register group, lcd driver and keyboard interface
在硬體方面,在完成計算器的功能模塊劃分的基礎上,對包括rc振蕩器、電源模塊、 lcd顯示驅動模塊、鍵盤介面、寄存器組、微程序控制器在內的各個功能模塊的系統結構和電路原理進行了分析,掌握了它們的設計方法。The contribution of this dissertation includes : ( 1 ) a register sensitive unrolling ( rsu ) algorithm is presented, which evaluates unrolling factors considering register pressure to allow more loops to be software pipelined ; ( 2 ) a stacked register allocation ( sra ) algorithm is presented to allocate free stacked registers to variants requiring static registers
本文的主要貢獻包括以下幾個方面: ( 1 )提出了一種寄存器敏感的循環展開因子( rsu )演算法。該方法通過寄存器壓力的分析,重新計算循環展開因子,避免了過度展開而導致的寄存器壓力過大問題,從而盡可能地保證軟體流水的順利進行; ( 2 )提出了一種堆棧寄存器分配( sra )演算法。By default, the compiler uses the coprocessor s 80 - bit registers to hold the intermediate results of floating - point calculations
默認情況下,編譯器使用協處理器的80位寄存器保存浮點計算的中間結果。With software and hardware co - design method, this paper proposes an algorithm to calculate register lifetime in programs, and the control of writing results back into rf is implemented through an enable control signal provided by instruction encoding at compile time
基於軟硬體協同設計的思想,在研究局部變量生存期演算法的基礎上,本文提出了通過編譯器指令編碼實現對硬體結構的使能控制,即控制流水輸出結果是否寫回寄存器文件,以減少對寄存器文件的寫次數,從而降低寄存器文件埠的讀寫壓力。This paper presents an architecture based - on shift register array, which can be used for the search for the two search pattern simultaneously. this architecture was inspired by the vlsi architecture for diamond - search - pattern - based algorithms. it exploits the overlap of reference data among the search points to reduce data memory accesses which are the most power consuming operations
其基本思想是利用搜索點之間的參考數據重疊的特徵,把需要用於多個搜索點計算的參考數據存儲在移位寄存器陣列中,通過移位操作來滿足不同搜索點的計算需要,大大降低了數據存儲器訪問次數,從而減少了運動估計中功率消耗最大部分的操作。Sse and sse2 instructions will be used for some scalar floating - point computations, when it is determined that it is faster to use the sse sse2 instructions and registers rather than the x87 floating - point register stack
時,優化程序將選擇何時以及如何使用sse和sse2指令。當確定使用sse / sse2指令和寄存器肯定要比使用x87浮點寄存器堆棧更快時, sse和sse2指令將用於某些標量浮點計算。3. realize the interface between pci9054 and the pci bus, including the bus arbitration, read and write of the registers, the configuration of the eeprom, the dma transfer, interrupt response and so on
3 .實現pci9054與計算機pci總線的介面,包括總線仲裁,寄存器讀寫操作, eeprom的配置和下載, dma傳輸,中斷響應等功能。Calculation for the data from simulation shows that power dissipation of det shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart set shift register
對模擬所得數據的計算結果表明,與實現相同功能的單邊沿移位寄存器相比,由於工作頻率減半,雙邊沿移位寄存器的功耗有明顯降低。Calculation for the data resulted from simulation shows that power dissipation of det shift register can be reduced evidently because of using the clock with half working frequency, in comparison with its counterpart set shift register
對模擬所得數據的計算結果表明,與實現相同功能的單邊沿移位寄存器相比,由於工作頻率減半,雙邊沿移位寄存器的功耗有明顯降低。Set the last register with counted value
最後一個寄存器值存放計算好的輸入值。分享友人