詳細邏輯設計 的英文怎麼說

中文拼音 [xiángxìluóshèjì]
詳細邏輯設計 英文
detailed logical design
  • 詳 : Ⅰ形容詞（詳細） detailed; minute Ⅱ名詞（詳細情況） details; particulars Ⅲ動詞1 （說明; 細說） tel...
  • 細 : 形容詞1 （條狀物橫剖面小） thin; slender 2 （顆粒小） in small particles; fine 3 （音量小） thin ...
  • 邏 : Ⅰ動1. （巡察） patrol 2. [書面語] （遮攔） blockⅡ名詞1. （巡察） patrol 2. [書面語] （山溪的邊緣） edge
  • 輯 : Ⅰ動詞（編輯; 輯錄） collect; compile; edit Ⅱ名詞（整套書籍、資料的各個部分） part; volume; division
  • 設 : Ⅰ動詞1 （設立; 布置） set up; establish; found 2 （籌劃） work out : 設計陷害 plot a frame up; fr...
  • 計 : Ⅰ動詞1 （計算） count; compute; calculate; number 2 （設想; 打算） plan; plot Ⅱ名詞1 （測量或計算...
  • 詳細 : detailed; minute; circumstantial; explicit
  • 邏輯 : logic
  • 設計 : devise; project; plan; design; excogitation; layout; layout work; styling
  1. This article contains three parts, five chapters. the first part introduces the incentive models of actual bonus stock synoptically, analyses the stock on hand, option shares and stock option, the three kind of important incentive models, on rights and incumbencies, value and the incentive guidance by contrast. the second part discusses the difficulties and influential factors in the design of technical bonus stock, quests for the incentive models of technical bonus stock, analyses superiority and inferior position in action, difference and interosculation between them, discusses the need and significance for the technical bonus stock reanimation in the middle - small technicalfilms. in order to make use of the technical bonus stock distribution mechanism fully, inspire the talent of technologists, encourage their devotion to films, we have some important discussion on the technical bonus stock distribution policy, introduce the distributed models of technical bonus stock, point out the questions in the excutive course, and offer the solution correspondingly. in the third part, we discuss the technical stock option design on middle - small technical films, and consider the logical thoughtfulness in the course of reanimation as follows : the more outstanding achievement for the powered man the more increase on special target the lower price on technical option premium the more profit the more effective reanimation. in the parameter, a set of detailed program is designed, which includes establishment of incentive fund, institution of merit system for the plan ' s grantors, award of stock option, determination of premium, so as to reduce random in the incentive course, have a great effect on the mormative management for the

    本文內容共分為五章三大部分，第一部分概括性地介紹了現行股權激勵方式，對現股、期股和期權這三種重要的激勵方式，從權利義務、價值和激勵導向三個方面進行了對比分析；第二部分探討了技術股權設計的難點和影響因素，討論了我國中小科技企業技術股權激勵的方式，分析它們在激勵中的優勢和不足，以及它們之間的區別與聯系，並對中小科技企業實施技術股權激勵的必要性和意義進行了探討。在文中還重點討論了中小科技企業技術股權分配的策略，介紹了技術股權紅利分配方式，指出在技術股權激勵過程中應注意的問題，並提出相應的解決辦法，目的在於充分利用技術股權分配機制，來激發技術人員潛在的創新能力，激勵他們為企業作貢獻；第三部分著重探討了中小科技企業技術股份期權的方案設計，在激勵方面，按照技術期權獲受人的業績越突出特定的指標增長越快行權價越低獲利越多激勵效果越好的邏輯思路進行考慮；在參數設計方面，對技術期權計劃中激勵基金、授予和考核、行權價格等參數進行了詳細地分析設計，旨在減少技術期權激勵過程中的隨意性，為中小科技企業的規范化管理起到一定的指導和借鑒作用。
  2. By thorough analysis and synthetize this paper made a frame of the system of intelligent instrument and its hardware structure. as followed, this paper depicted design details of intelligent instrument " s hardware, it included the design of interface circuit, data commutations and digital logic of dsp, mcu, internet ' s chip and isp ' s apparatus etc., and have designed schematic map and circuit. so it accomplished the full design of hardware / software of the new type intelligent instrument

    本文具體給出了新型智能儀器硬體結構及實現，描述了智能儀器硬體設計細節，包括數字信號處理器、單片機、 internet接入晶元、可編程數字/模擬器件等在新型智能儀器中的介面電路設計、數據通信設計和數字邏輯設計等，詳細地給出了設計原理圖和電路圖；給出了新型智能儀器的軟體設計細節，從而完成了新型智能儀器完整的軟硬體設計。
  3. In the fourth chapter, it expatiates the whole steps of implement. in the fifth chapter, it recommends the testing on the web and local area network. in the last chapter, it summarizes the merit and shortcoming of the system and puts forward the orientation of improvement

    第一，介紹了考試系統設計開發的背景與意義;第二，論述了與考試系統有關的理論和技術基礎:第三，從邏輯設計角度對系統進行細致的介紹;第四，詳細闡述了系統實現的全過程;第五，介紹了在網際網路上對系統進行測試與試用的情況:第六章，對系統的優缺點進行了總結，提出了改進的大致方向。
  4. Secondly, the paper describe the principle of atm network, and the function of ' sar " ( segmentation and reassembly ) and the format of packet aal5, and introduce the basic idea of ipoa, and the design project and implementing of the control chip. later, the paper introduce the logic function and operational principle of packet buffer control chip and prove the feasibity and correctness of the arithmetic. at last the paper introduce crc - 32 arithmetic based on look up and implement it with hardware

    接著詳細論述了核心路由器atm網路實現的原理，包括「 sar 」 （ segmentationandreassembly ）功能和aal5報文的格式， ipoa基本思想，以及控制晶元的設計方案和實現途徑等。然後又論述報文緩存區控制晶元的工作原理和邏輯功能等，並對演算法的可行性，正確性等進行論證。最後介紹了一種基於查表的crc - 32演算法的原理及其硬體實現。
  5. In addition, make out in detail the design on inner combination logic and time logic of fpga, including series - parallel conversion, data selector, counter, flip - latch, timer, encoder, etc. at one time, not only pursuit flow of the data gathering system is illuminated, but also make use of in reason and effectively inner ram resource of fpga and build it in ping - pong framework

    另外，詳細的介紹了fpga內部的組合邏輯和時序邏輯的設計方案，包括串並轉換、數據選擇器、計數器、鎖存器、定時器、譯碼器等。並闡述了數據採集系統的工作流程，而且合理有效地使用了fpga內部的ram資源，將其構建成乒乓式結構。
  6. Secondly, the composition and function of expander board is introduced, the paper describes a detail developing process of selecting component, design interface circuit, protract pcb with protel and design pci interface logic and user ' s logic. with ahdl and max + plus. in addition this paper discusses how to debug pci board, and give the simulation waveform and the result of debug. on the base of all functions is ture, this paper introduce the config registers and memory of bu - 61580, realize the interrupt function and communication based on mil - std - 1553b

    首先分析了擴展板的組成、功能，對pci介面邏輯和擴展板的內部邏輯進行詳細設計，並根據其資源要求進行器件選擇，然後使用protel工具進行電路板的製作。另外，本文還介紹了擴展板的調試方法，給出了邏輯模擬波形和調試結果。在此基礎上，本文闡述了協議晶元的配置方法，實現了1553b通訊擴展板間的通訊及中斷功能，達到了開發技術指標。
  7. It implements filter groups design, wide range linear automatic gain control design, and the programmed logic device design based on vhdl, and discuss their application in initial radar system in details

    其中包括分段濾波器的設計技術，寬線性自動增益控制agc電路的設計技術，以及基於vhdl語言的可編程邏輯器件的設計技術，並對其在數據採集系統中的應用作了詳細的討論。
  8. On basis of the development of modern control technology and apply of the network technology and locale bus - mastering technology ， this text analyzes the essential element for produce of wire - roll mill : principle of assign for speed ; expatiates in detail on the network structure and communication protocol of ethernet and profibus - dp ; concretely describes the forms of control system configuration ， the function and features of its software and hardware designs ; also, introduces mainly control function of control system, ， for example ， sequence control 、 loop control 、 fly shear control and operation and monitor function etc

    基於現代控制技術的發展、網路技術以及現場總線技術的應用，本文分析了線材生產的基本要素：速度的分配原則；分析了工業以太網ethernet和現場總線profibus - dp的結構和通訊協議。主要說明plc控制系統的組織結構形式，系統的軟硬體設計的功能和特點。同時，詳細介紹了控制系統的主要控制功能，如邏輯控制、活套控制、飛剪控制以及操作監控功能等等。
  9. In the next paragraphs, the functions software environment, logic - map, design, and key parts of the system are described

    接下來我們將從系統的功能特點、運行環境、運行邏輯圖、系統的詳細設計、主要關鍵技術的等方面進行介紹。
  10. In this paper, the belief logic system gny and it ' s related implementation tool spearii are utilized, ssl protocol is a focused instance, then the detailed analysis procedure from initial protocol model to various evolution protocol models is given, later the final evolution protocol model and ssl protocol are contrasted and thus the security analysis conclusion is drawn for ssl. during the analysis procedure two practical security authentication solutions are designed based on evolution protocol models

    本文採用著名的信念邏輯gny邏輯系統及其相關的形式化工具spear ，以ssl協議為分析實例，詳細闡述了從初始協議模型到各個進化協議模型的分析過程，並將最終的進化模型與ssl協議作比較，給出ssl協議的安全分析，同時在分析過程中以協議模型為基礎設計了兩個實用的安全認證方案。
  11. In addition, a novel heuristic approach which we called “ improved simulated annealing algorithm ” is proposed for bounding maximum and minimum leakage power. 2. a design method for low power clock network is proposed

    通過對高性能通用處理器中時序邏輯特點的詳細分析，提出採用帶門控使能的多比特觸發器設計方法來降低時鐘功耗。
  12. Describes the design and realization of partial run - time reconfigurable fpga in detail. in order to reduce the affect of the reconfiguration time on system execution time, mostly static circuit design method in logical design stage and incremental routing method in component implementation stage are proposed. the fft parallel processing algorithm is examined through vvp platform

    本章詳細闡述了基於vvp平臺的多sharc功能插板的具體硬體實現，以動態重構fpga設計為核心，論述了局部動態重構fpga設計流程和方法，提出了極大靜態電路邏輯設計方法和遞增式布線方法，以達到減小動態重配置時間，提高系統運行效率的目的。
  13. The system design includes information model, function design and dada - base logical relation. the information model is established by entity - relation method, and the e - r picture is ploted, and the in - out diagram is gived out ; the fuction designed is established by idef0 method, the subsystems are designed according to the model in detail, we give out the explaining document and explain the calculation method for the model ; we design the data - base logical relation by the above models, decide the distributing and partition the relation diagram of the data - base, then define the logical structure of the diagrams

    其中信息建模採用實體-聯系的方法建立系統的信息模型，並用idef1x圖表示出該信息模型，同時給出電泵物資管理系統輸入輸出信息表；功能設計用idef _ 0方法建立電泵物資管理系統分系統功能模型，參照功能模型對內部各子系統進行詳細設計，給出分系統功能模塊的詳細說明書及相應功能演算法描述；數據庫邏輯設計依據系統分析結果、信息模型及功能模型，確定電泵物資管理系統數據庫分佈，劃分數據庫內部關系表，定義表的具體邏輯結構。
  14. Besides the logic design, we also divide our system into two parts - background database and forward user ' s interface, and detail the technology design of the two parts respectively

    除了對系統經行了邏輯設計，在技術上我們將系統分為后臺的數據庫與前端用戶程序兩大部分分別經行了詳細的論述。
  15. This paper deeply discusses the content and structure of process data, establishes a xml ( extensible markup language ) process data model, and presents the xml expression of the special process data. combined with the application of nanqi capp system, some disposal mechanism and methods are proposed on the basis of the xml data model, such as data exchange, data transport, data storage, data query, data security and data integration. at the end of this paper, the realization of several capp functional modules are expounded to interpret the disposal details of xml process data

    本文詳細論述了工藝數據的內容和結構，通過概念建模和邏輯設計建立了基於xml標準的工藝數據模型，給出了特殊工藝數據的表達方式和應用描述，在此基礎上結合企業b s模式capp系統的開發提出了針對xml工藝數據的一些處理機制和方法：數據轉換、數據傳輸、數據存儲、數據查詢、數據安全和數據集成等，並通過工藝統計和基本信息查詢兩項capp功能模塊的實現過程對此作了具體闡述。
  16. We pointed out the features of this infrastructure, analyzed the basis of modern applied software - mvc mode, elaborated the j2ee system infrastructure used by this system, and analyzed the integrated infrastructure system. then from the system ' s real requirement, with the object - oriented method, we used an advanced modeling tool - rose to model the system ' s requirement and logic design, then finally implemented the system design. this system uses powerdesigner to do the data modeling, jbuilder as the development tool, and struts framework to realize the separation of the expressing layer, the logic layer and the data layer

    通過研究和開發寬帶boss ，了解了有關boss的基本概念、模型、發展現狀及發展趨勢；然後分析了現代應用軟體的架構： b s架構，指出了此種架構的特點，並分析了現代應用軟體架構的基礎? ? mvc模式，詳細介紹了本系統所採用的j2ee體系架構，對組成本系統的整體架構體系進行分析；隨后從本系統的實際需求出發，以面向對象的方法，採用先進的建模工具rose對系統的需求及邏輯設計進行建模；最後對系統設計加以實現，本系統用powerdesigner對數據建模，以jbuilder為開發工具，採用struts框架實現表示層、邏輯層及數據層的分離，數據層採用數據持久化技術hibernate ，從而可以隱藏訪問數據源的數據訪問api ，簡化開發。
  17. On the basis of the analysis on the developed pci logic, the desinger improve upon the pci interface logic according to the project ' s requirments. moreover, the dissertation explains the composition, functions and internal design of the pci board

    在詳細分析了已有的pci介面邏輯設計的基礎上，根據本課題的具體需要做出了改進。本文分析了數據通信介面板的組成、功能，描述了介面板內部邏輯的詳細設計。
  18. The vxibus c - size and i, q channels are employed in this module design, and the sampling rate in each channel reaches 500mhz. the memoty deep of the system is 2mb each channel and cpu is high - speed embedded cpu ( powerpc ). the timing and logic function are fulfilled by fpga. after the disscusion of signal adjusted, the detailed scheme of this module design have been showed. in this design, there is much logic function design, and it is very strict with the hardware language program. so the basic flow of hardware program design and several very important methods of high speed logic function design, which is described by vhdl, are introduced. also, expatiated the inner modules structure of fpga for forepart circuit, the keystone and difficulties of the design. the design of high - speed pcb is another difficuty of realizing high - speed data acquisition system, and it is very important. the timing simulating results of several pivotal modules are depicted. high - speed signal paths are terminated to match the characteristic impedance. the design undergoes integrity analysis and software simulation

    在本模塊的設計中，有著大量的邏輯設計，對硬體語言程序的編寫要求比較高，因此，文中介紹了硬體程序設計的基本流程，以及幾種基於vhdl硬體語言設計在高速邏輯設計中非常重要的方法。同時闡述了本模塊設計的前端fpga的內部模塊結構，設計的重點、難點，並給出了重要模塊的時序模擬結果。高速pcb的設計也是目前實現高速數據採集系統的難點和重點，文中詳細的闡明了高速pcb設計中的注意點，以及作者在設計本模塊時的經驗和心得。
  19. A complete vvp instrument consists of one enhanced main board and several plug - in boards, which is suitable for constructing basic instruments ( no cpu ), typical instruments ( a single cpu ) and advanced instruments ( multi - dsp )

    本章詳細闡述了vvp平臺的設計思想、體系結構以及vvp控者模塊邏輯設計的實現。
  20. The hardware design for the system is introduced in detail, including dsp mini system, a / d conversion circuit and communication interface, also the logic design for cpld is described. and the software design is described in detail as followed, the software for the system is mainly implemented in dsp including the controls of the data - acquisition, data processing and submitting

    詳細介紹了系統的硬體設計和實現方案，包括dsp最小系統， a d轉換通道，通信介面等；論述了如何使用cpld作為dsp與其外圍器件之間的介面，並給出了詳細的cpld內部邏輯設計過程。
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